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參數(shù)資料
| 型號(hào)： | HIP4020IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 30000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | STEPPER MOTOR CONTROLLER, 1.5 A, PDSO20 |
| 封裝： | PLASTIC, MS-013-AC, SOIC-20 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 65K |
| 代理商： | HIP4020IB |
1
HIP4020
Half Amp Full Bridge Power Driver
for Small 3V, 5V and 12V DC Motors
Description
In the Functional Block Diagram of the HIP4020, the four switches
and a load are arranged in an H-Configuration so that the drive volt-
age from terminals OUTA and OUTB can be cross-switched to
change the direction of current flow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches Q1 and Q4 are conducting or in an ON state when current
flows from V
DD
through Q1 to the load, and then through Q4 to termi-
nal V
SSB
; where load terminal OUTA is at a positive potential with
respect to OUTB. Switches Q1 and Q4 are operated synchronously
by the control logic. The control logic switches Q3 and Q2 to an open
or OFF state when Q1 and Q4 are switched ON. To reverse the cur-
rent flow in the load, the switch states are reversed where Q1 and Q4
are OFF while Q2 and Q3 are ON. Consequently, current then flows
from V
DD
through Q3, through the load, and through Q2 to terminal
V
SSA
, and load terminal OUTB is then at a positive potential with
respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A and B
Input Controls. The ILF output is an Over-Current Limit Fault Flag Out-
put and indicates a fault condition for either Output A or B or both. The
V
DD
and V
SS
are the Power Supply reference terminals for the A and
B Control Logic Inputs and ILF Output. While the V
DD
positive power
supply terminal is internally connected to each bridge driver, the V
SSA
and V
SSB
Power Supply terminals are separate and independent from
V
SS
and may be more negative than the V
SS
ground reference termi-
nal. The use of level shifters in the gate drive circuitry to the NMOS
(low-side) output stages allows controlled level shifting of the output
drive relative to ground.
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HIP4020IB
-40 to 85
20 Ld SOIC
M20.3
Features
Two Independent Controlled Complementary
MOS Power Output Half H-Drivers (Full-Bridge)
for Nominal 3V to 12V Power Supply Operation
Split
±
Voltage Power Supply Option for Output
Drivers
Load Switching Capabilities to 0.5A
Single Supply Range +2.5V to +15V
Low Standby Current
CMOS/TTL Compatible Input Logic
Over-Temperature Shutdown Protection
Over-Current Limit Protection
Over-Current Fault Flag Output
Direction, Braking and PWM Control
Applications
DC Motor Driver
Relay and Solenoid Drivers
Stepper Motor Controller
Air Core Gauge Instrument Driver
Speedometer Displays
Tachometer Displays
Remote Power Switch
Battery Operated Switch Circuits
Logic and Microcontroller Operated Switch
June 1997
Pinout
HIP4020 SOIC
TOP VIEW
Block Diagram
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
NC
ILF
B2
ENB
B1
V
SS
ENA
A1
A2
NC
NC
NC
OUTB
V
SSB
V
SSA
OUTA
V
DD
NC
V
DD
NC
V
SSB
V
DD
OUTB
L
OUTA
B1
B2
ENB
A1
A2
ENA
ILF
V
SS
V
SSA
Q1
Q3
Q2
Q4
C
L
C
L
I
SENSE
T
SENSE
I
SENSE
I
SENSE
I
SENSE
O
L
File Number
3976.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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