- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384421 > HIP2500 (Intersil Corporation) () PDF資料下載
參數(shù)資料
| 型號： | HIP2500 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 81K |
| 代理商： | HIP2500 |
4-2
Description of the HIP2500
The block diagram of the HIP2500 is shown in Figure 3. The
HIP2500 contains both ground referenced and high voltage
bus referenced (floating) gate drive circuits. With the excep-
tion of level-translation circuitry communicating between the
upper driver circuit and the upper input control logic, the upper
and lower driver and control circuits are nearly identical.
Input Logic
The input logic of the HIP2500 incorporates pull-down circuits
which allow any of these inputs to be left open if they are not
used. The pull-down current is approximately 12
μ
A. As well
as electrostatic input protection, the inputs are Schmitt-buff-
ered and a level-translation circuit allows 5V logic inputs to
communicate with the downstream logic which drives the
gates of the power switches connected to the HIP2500. This
logic is nominally biased between 12V and 15V. An extra ben-
efit of the level-shifter is to provide input circuit noise immunity
by continuing to function even though the V
SS
terminal moves
with respect to the COM terminal from about -2.0V to
+V
CC
/2V. When attempting to lower the V
SS
terminal more
than -2.0V below COM, however, the HIP2500 will continue to
function, but heavy substrate current flows. Therefore one
should not attempt to deliberately shift the V
SS
and COM ter-
minals from each other.
The three inputs to the HIP2500; HIN, LIN and SD control
the floating high side driver, the low side (ground referenced)
driver and the “shutdown” functions, respectively, in accor-
dance with the timing diagram in Figure 5. The HO and LO
gate drive signals respond within a short (typically 400ns)
propagation delay of their respective HIN and LIN signals. In
half-bridges where deadtime is required to prevent conduc-
tion overlap or “shoot-through”, the HIN and LIN input com-
mands must be appropriately spaced by the user. For
example in a typical half-bridge configuration such as in Fig-
ure 4, where the upper and lower switches are series con-
nected between the high and low sides of the power bus, the
user must ensure that one switch is completely off before
turning on the other. If this precaution is not followed, con-
duction overlap will occur in both switches, usually leading to
destruction of one or both power switches and possibly the
HVIC. Occasionally, a few passive components added to
delay switch turn-on without delaying turn-off can effectively
control shoot-through (see the diode resistor parallel combi-
nation in Figure 4). As power levels and power switch
devices
become
larger,
active
techniques may be a more appropriate means for providing
turn-on blanking of one switch while turning off the other.
rather
than
passive
Two independent latches provide a means to inhibit the HO and
LO outputs from going high whenever a Shutdown pulse has
occurred. Resetting of the latches is accomplished at the
moment that the respective HIN and LIN signals go low, pro-
vided that the SD input is also low.
The timing diagram shown below will help to make operation of
the input latch and shutdown logic more clear. The arrows show
that at the instant the HIN and/or LIN inputs go low the shut-
down latch is reset. Subsequent high signals on HIN or LIN will
then be passed on to the edge logic and level-translation cir-
cuits before final processing by the output driver circuits.
Edge Logic
After the HIN and LIN input signals are squared up by the
input logic, they are processed further by the Edge Logic.
The purpose of the Edge Logic is to create short pulses to
be further processed by the upper and lower output driver
logic. There are two Edge circuits; one for the floating driver
and one for the COM referenced driver.
V
SS
V
DD
HIN
LIN
SD
LEVEL
SHIFT
LOGIC
UV
S
R
LATCH
DRIVER
DRIVER
V
CC
V
B
V
S
HO
LO
COM
FIGURE 3. HIP2500 FUNCTIONAL BLOCK DIAGRAM
UV
V
CC
SYSTEM
CONTROL
SD
LIN
V
SS
COM
V
S
V
DD
HIN
V
CC
LO
V
B
HO
C
F
D
F
TO
LOAD
R
G
R
G
H
V
H
FIGURE 4. SIMPLIFIED SHOOT-THROUGH CONTROL
SD
HIN
LIN
HO
LO
FIGURE 5. INPUT TIMING DIAGRAMS
Application Note 9010
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP4011 | Three Phase Brushless DC Motor Controller |
| HIP4011IS | Three Phase Brushless DC Motor Controller |
| HIP4020 | 30000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| HIP4020IB | 30000 SYSTEM GATE 3.3 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN |
| HIP4080 | 80V/2.5A Peak, High Frequency Full Bridge FET Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP2500IB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP-2500IB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP2500IB96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP2500IP | 制造商:HARRIS 制造商全稱:HARRIS 功能描述:Half Bridge 500VDC Driver |
| HIP2500IP1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。