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參數(shù)資料
| 型號(hào)： | HIP2500 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 81K |
| 代理商： | HIP2500 |
4-3
Each Edge circuit has two inputs and two outputs. One output
goes high coincident with a rising-edge signal from the input
logic. The other output goes high coincident with a falling-
edge signal from the input logic. Both outputs are short pulses
which minimize the power dissipation of the Level-translation
transistor. Although there is no lower level-translation transis-
tor, the lower Edge circuit nonetheless helps provide the nec-
essary symmetry between upper and lower switch delays.
The second input to each Edge circuit comes from the lower
Undervoltage (U/V) circuit. In the event of a lower undervolt-
age condition (i.e., a low V
CC
), the outputs of both upper and
lower Edge circuits issue turnoff pulses.
Level-Translation
The upper Edge circuit issues turnon and turnoff pulses to
the Level-Translation circuit. This circuit mainly consists of
two high voltage npn transistors which conduct very narrow
current pulses to the upper (floating) gate drive circuit.
Communication with the upper switch drive logic creates a
potential for excessive power dissipation. By using only very
short level-shift pulses from the V
SS
referenced logic
through the high voltage level-shift circuit to a latch in the
upper switch driver, level-shifting power dissipation can be
minimized. Two high voltage level-shift transistors are
required to control the upper switch, one for turnon pulses
and one for turnoff pulses. The level-shift current pulses are
robust in order to provide noise discrimination, but are also
very short so as to avoid significant power dissipation.
Driver Circuits
The driver circuits for the upper and lower gate drives are
identical, except for the settings of the delay-matching cir-
cuits. Delay matching makes it easier to equalize the
dead-time between upper and lower switch conduction peri-
ods. A secondary benefit of delay matching is to provide
duty-cycle equalization of the input waveform and the output
waveform at the V
S
terminal. Delay-matching imbalance
becomes more noticeable at high switching frequencies.
The HIP2500 uses P-Channel MOSFETS in the output stage
of the drivers for sourcing gate current to the power devices
and is unique in its ability to drive the gates of the upper and
lower switches to the full applied bias voltage. Similarly N-
Channel devices have been employed for sinking current from
the gates of the power devices. This allows complete utiliza-
tion of the supply voltage and power device gate voltage will
be unaffected by changes in driver threshold voltage varia-
tions. The approach employed in the HIP2500 also avoids the
additional power dissipated due to the threshold voltage drop
associated with source-follower topologies. At high operating
frequencies this can be significant.
The sink and source currents of the gate drivers are fully
capable of supplying peak currents of at least 2.0A, which
means that a power MOSFET device with 3000pF gate
source capacitance can be fully charged in 25ns. Discharge
of the gate source capacitance will be slightly more rapid,
since r
DS(ON)
of the sink driver is about 10% less than the
source driver.
The high side driver section is built into an “isolation tub”
which is capable of floating +500V
DC
above substrate poten-
tial with respect to power ground (COM). V
S
is the common
potential for the upper drive circuitry and is the most negative
voltage within the floating tub. V
B
is the positive rail within the
floating tub and is usually 12V to 15V above V
S
. The gate
drive output, HO swings between V
S
and V
B
according to the
state of the HIN input pin.
Under-Voltage Lockout
The HIP2500 is protected internally from insufficient boot-
strap supply voltage (in the case of the upper floating driver)
and insufficient bias supply voltage (in the case of the lower
driver). Also the HIP2500 will not turn on either of the
switches should the high voltage supply be brought up
before the low voltage bias supply power.
As mentioned previously under Edge Logic, the lower under-
voltage lockout blocks drive to both upper and lower power
switches. The reason for turning off both switches when only
the lower bias supply is below its U/V trip setpoint is that the
upper bias supply is refreshed from the lower supply. There-
fore the floating supply can never be any higher than the
voltage on V
CC
. The U/V latches are reset upon reestablish-
ment of proper bias supply voltage level and a low transition
of the LIN and/or HIN signals.
The upper logic circuit has a separate undervoltage circuit
which controls only the gating of the upper (floating) switch.
The switch is latched off upon occurrence of an undervolt-
age condition across the bootstrap capacitor. Latching is
reset when the undervoltage condition goes away. A subse-
quent “on” pulse from the HIN terminal will turn on the upper
switch. The HIN terminal must have previously gone low in
order for the Edge circuit to issue an on pulse to the upper
driver logic. Latching the drivers off in the event of an under-
voltage condition eliminates the potential of entering a
limit-cycle condition. To avoid U/V trip, the circuit designer
must pick a value for bootstrap capacitance which supports
the bias current requirements of the floating supply without
tripping the under-voltage circuit. Guidance on choosing the
bootstrap capacitor can be found under “Design Consider-
ations” later in this note.
Design Considerations
The designer must deal with the following areas to success-
fully apply the HIP2500:
Bias Supply Design
Propagation Delay Issues
Power Dissipation, Thermal Design
Bias Supply Design
The design of the HVIC bias supply is not particularly diffi-
cult. First establish the desired gate voltage for the power
switch. For most MOSFETs and IGBTs there is a point at
which increasing gate-to-source voltage yields no significant
reduction in switch forward drop. Usually this occurs at about
8V to 9V. Avoid overcharging the gate of the power switch
Application Note 9010
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