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參數(shù)資料
| 型號(hào)： | HIP2500 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 81K |
| 代理商： | HIP2500 |
4-6
r
DS(ON)
of the power switch. The r
DS(ON)
of the IRF450 is
approximately 0.3
at 10A. To the above must be added the
r
D
of the bootstrap diode, which is about 1.1
max. at 1.0A.
Assuming another 0.1
series resistance for the capacitor
and circuit board traces, then a total resistance of about
1.5
is in the bootstrap loop. The charge time constant of
the bootstrap capacitor is the product of the loop resistance
of 1.5
and the bootstrap capacitance of 0.33
μ
F. This yields
0.5s charging time constant. If 2 time constants are reserved
for charging, then the bootstrap capacitor will only charge to
about 86% of the V
CC
supply. In 3 time constants it will
charge to 95% of the V
CC
supply. Keep in mind that the U/V
circuit maximum trip level is 9.99V. This fact will impact the
choice of capacitor and the allotted refresh time. If we
assume 3 time constants are sufficient, then to drive the
IRF450 to 15V would require a V
CC
voltage of 15/95%, or
15.8V.
Propagation Delay Issues
The HIP2500 is designed to enhance rejection of noise from
external circuits. Several filters and signal integrators are
used to accomplish the noise rejection resulting in input to
output propagation delays on the order of 400ns. Much of
the propagation delay associated with the upper switch is a
result of the level-shift circuit. To better match the upper and
lower propagation delays, additional delays were inserted in
the lower circuit. Filter and matching circuits were designed
to provide tracking of upper and lower propagation delays
over temperature and bias voltage changes. In practice very
good tracking is achievable, with the “on-delays” increasing
approximately 150ns over temperature and the “off-delays”
increasing about 100ns over temperature. Because the
absolute propagation delays of the upper and lower circuits
were not exactly matched, it is necessary to call attention to
them so that the circuit designer can compensate for them.
The variation in propagation delays manifests itself in vary-
ing dead-times. Dead-time is defined as the time between
the fall of one of the gate voltage waveforms and the rise of
the other gate voltage waveform. The midpoints in the gate
voltage waveforms are used to time the measurement. A
1000pF load is used to simulate the “typical” power device
gate-source load. It is possible, when turning off the upper
and turning on the lower switch, to experience a slightly neg-
ative dead-time of less than 50ns. The minimum dead-time
experienced going the other way (turning off the lower and
turning on the upper switch) is 95ns. The best way to guar-
antee that proper dead-time always exists is to insure that
the signals driving the LIN and HIN inputs of the HIP2500
always include dead-time. This will prevent shoot-through
conduction
and
possible
Dead-time can be enhanced by using the technique shown
in Figure 4. With proper choice of series gate resistance, it
may be possible to completely mask the effects of dead-time
mismatch.
power
device
destruction.
Power Dissipation and Thermal Design
The power dissipated in the HIP2500 can be lumped into
static and dynamic losses. The static losses are limited to
bias current losses for the upper and lower sections of the
IC. The lower bias current, I
QCC
, is typically 1.5mA at 25
o
C.
The upper bias current, I
QBS
, is typically 300
μ
A. At 15V
bias, the total power dissipation is less than 30mW. Since
I
QDD
is typically only 100pA, the losses associated with this
bias current is insignificant.
The switching losses are those losses associated with turn-
ing on and off the upper and lower power devices. These are
the significant losses within the HIP2500. The switching
losses can be further broken down into the following compo-
nents:
Low Voltage Gate Drive Charge Transfer
High Voltage Level-Shifter
High Voltage Tub-Capacitance Charge Transfer
The low voltage gate drive charge transfer power loss is the
most significant of the 3 loss components above. Equation 3
describes the power loss attributable to the upper and lower
switch gate charge transfer as a function of bias supply, V
CC
,
switching frequency, f
PWM
, gate charge, Q
G
, and the
HIP2500 internal CMOS charge transfer losses, Q
INTERNAL
,
of the driver stages. Unless the gate charge of the power
device is very small, Q
INTERNAL
is not very significant.
PSWLO
The high voltage level-shifter power dissipation, Equation 4,
is much more difficult to analyze. The reason that this equa-
tion is hard to solve is that the level-shift current pulses, i
ON
and i
OFF
, and the phase voltage, v
SHIFT
, are all functions of
time and the phase voltage moves in response to power
switch turnon and turnoff, which is also dependent on the
power MOSFET or IGBT used. The i
ON
pulse, for example,
may come and go before any movement in the phase volt-
age is evident and therefore dissipate very little energy. The
phase voltage usually will be a maximum when the i
OFF
pulse comes, so the off pulse may dissipate quite a bit of
energy.
T
∫
Finally, the tub capacitance power dissipation can be calcu-
lated from Equation 5. The “tub” is the p-n junction which iso-
lates all of the circuitry associated with the high side driver
from all of the low side circuits. The calculation is a charge
transfer energy calculation very similar to that used for the
gate charge transfer, except that the charge is much smaller
and the voltage, v
SHIFT
, much larger. This capacitance
unfortunately varies with voltage and it is difficult to measure.
The tub capacitance charge transfer losses are shared
between resistances both internal and external to the
HIP2500. A conservative approach, however, assumes all of
the losses are dissipated within the HIP2500.
fPWM
2fPWMQG
QINTERNAL
+
(
)
VCC
=
(EQ. 3)
(EQ. 4)
PSHIFT
1
T
---
iON
iOFF
+
(
)
0
vSHIFTdt
=
(EQ. 5)
PTUB
CTUBV2
=
Application Note 9010
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