參數(shù)資料
型號(hào)： HFA3860BIV96
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： nullDirect Sequence Spread Spectrum Baseband Processor
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁(yè)數(shù)： 34/40頁(yè)
文件大?。?/td> 272K
代理商： HFA3860BIV96
4-34
Bits 7:0
Test Bus Address = 10h
NCO Test Hi Rate,
tests the NCO in the high rate tracking section.
Test 7:0 = NCO Accum (19:12)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 11h
FREQ Test Hi Rate,
tests the NCO lag accumulator in the high rate tracking section.
Test 7:0 = Lag Accum (18:11)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 12h
Carrier Phase Error Hi Rate
Test 7:0 = Carrier Phase Error (6,6:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 13h
I_ROT Hi Rate,
tests the I Channel phase rotation error signal.
Test 7:0 = I_ROT (5,5,5:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 14h
Q_ROT Hi Rate
Test 7:0 = Q_ROT (5,5,5:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 15h
I_A/D, Q_A/D,
tests the I and Q Channel 3-bit A/D Converters.
Test 7:6 = 0
Test 5:3 = I_A/D (2:0)
Test 2:0 = Q_A/D (2:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 16h
XOR Hi Rate,
Factory Test Only
Test 7:0 + TEST_CLK = 9 bits of registered XOR test data from the high rate logic.
Bits 7:0
Test Bus Address = 17h
XOR Fast,
Factory Test Only
Test 7:0 + TEST_CLK = 9 bits of registered XOR test data from the low rate logic.
Bits 7:0
Test Bus Address = 18h
Timing Test,
tests the receiver timing.
Test 7 = JMPCLK
Test 6 = JMPCNT
Test 5 = SUBSAMPLECLK
Test 4:0 = MASTERTIM (4:0)
TEST_CLK = Sample CLK
Bits 7:0
Test Bus Address = 19h
A/D Cal Accum Lo,
tests the lo bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (8:0)
Bits 7:0
Test Bus Address = 1Ah
A/D Cal Accum Hi,
tests the hi bits of the A/D cal accumulator.
Test 7:0+TestCLK = A/D Cal Accum (17:9)
Bits 7:0
Test Bus Address = 1Bh
Freq Accum Lo,
tests the frequency accumulator of the low rate section.
Test 7:0+TestCLK = Freq Accum (15:7)
Bits 7:0
Test Bus Address = 1Ch
Slow XOR,
Factory Test
Test 7:0 = 8 bits of registered XOR test data from the low rate logic
TEST_CLK = SUBSAMPLECLK
Bits 7:0
Test Bus Address = 1Dh
SQ2 Monitor Hi
- SQ3 if SQ3 used for antenna diversity
Test 7:0 = SQ2 (15:8)
TEST_CLK = pulse after SQ is valid
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued)
Supplies address for test pin outputs and Test Bus Monitor Register
HFA3860B
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參數(shù)描述
HFA3860IV 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:
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