參數(shù)資料
型號： HFA3860BIV96
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： nullDirect Sequence Spread Spectrum Baseband Processor
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁數(shù)： 29/40頁
文件大?。?/td> 272K
代理商： HFA3860BIV96
4-29
Bit 1
MD_RDY Start. Sets where MD_RDY will become active.
0 = After SFD detect (normal). This allows the header fields to be enveloped by MD_RDY.
1 = After Header CRC verify and start of MPDU. Header data can be read from Configuration Registers.
Bit 0
TX and RX Clock
0 = Enable Gated clocks (normal). RX clock will come on to clock out header fields, go off during CRC and come back on for
MPDU data. Header rate is 1MHz, data rate is variable. TXCLK comes on after TXRDY active.
1 = Clocks start as soon as modem starts tracking and remain on until either header checks fail or until RX_ PE goes back
low. This is only usable in the 1 and 2MBPS modes. TXCLK comes on after TX_PE active.
CONFIGURATION REGISTER 2 ADDRESS (08h) TX AND RX CONTROL (Continued)
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
CONFIGURATION REGISTER 3 ADDRESS (0Ch) A/D CAL POS
Bits 0 - 7
This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D reference.
The larger the step the faster the A/D Calibration settles.
CONFIGURATION REGISTER 4 ADDRESS (10h) A/D CAL NEG
Bits 0 - 7
This 8-bit control register contains a binary value used for the negative increment for the level adjusting circuit of the A/D
reference. The number is programmed as 256 - the value wanted since it is a negative number.
CONFIGURATION REGISTER 5 ADDRESS (14h) CCA ANTENNA CONTROL
Bit 7
Selects definition of CR 16 and CR 17
0 = registers CR 16 and CR 17 defined as Signal definition fields
1 = those registers hold the cover code for the CCK modulation
Bit 6
Reserved, set to 0
Bit 5
0 = Normal
1 = A/D timing adjustment during acquisition, deassertion of RxPE required to activate.
Bit 4
0 = Normal
1 = Delayed bit sync accumulation
Bit 3
0 = Normal
1 = Use multipath antenna selection (SQ3)
Bit 2
RX Diversity
0 = Off
1 = On
Single antenna, can use A or B (see bits 1:0).
Antenna switches during acquisition every 16 us. Starts cycle on antenna defined by bits 1:0.
Bits 1:0
CCA Antenna mode. Defines the antenna to be used at the start of acquisition for CCA checking and for subsequent
transmission. TX antenna is always the same as used to check CCA. Controls antenna selection via the ANT_SEL pin.
00 = Use last Receive antenna for CCA checking and TX. Acquisition starts on the antenna which had a valid header on last
reception.
01 = Illegal State - Unknown Behavior
10 = Use antenna B for CCA and TX (single antenna). AntSel = 0
11 = Use antenna A for CCA and TX (single antenna). AntSel = 1
CONFIGURATION REGISTER 6 ADDRESS (18h) PREAMBLE LENGTH
Bits 0 - 7
This register contains the count for the Preamble length counter. Setup while TX_PE is low. For IEEE 802.11 use 80h. For
other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition
performance at the cost of greater link overhead. For dual receive antenna operation, the minimum suggested value is 128d = 80h.
For single receive antenna operation, the minimum suggested value is 80d = 50h. These suggested values include a 2 symbol TX
power amplifier ramp up. If you program 128 you get 130.
CONFIGURATION REGISTER 7 ADDRESS (1Ch) SCRAMBLER TAPS
Bit 7
0 = Normal, RX_PE Enables/Disables the internal receive clock. I = Internal receive clock is always enabled.
HFA3860B
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