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參數(shù)資料
| 型號(hào)： | HDMP-0482 |
| 英文描述： | Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
| 中文描述： | 八路細(xì)胞端口旁路電路CDR和數(shù)據(jù)有效檢測(cè) |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 149K |
| 代理商： | HDMP-0482 |
6
Table 3. Pin Definitions for HDMP-0482.
Pin Name
Pin
Pin Type
Pin Description
TO_NODE[0]+
TO_NODE[0]-
TO_NODE[1]+
TO_NODE[1]-
TO_NODE[2]+
TO_NODE[2]-
TO_NODE[3]+
TO_NODE[3]-
TO_NODE[4]+
TO_NODE[4]-
TO_NODE[5]+
TO_NODE[5]-
TO_NODE[6]+
TO_NODE[6]-
TO_NODE[7]+
TO_NODE[7]-
20
19
23
22
32
31
35
34
44
43
47
46
57
56
60
59
HS_OUT
Serial Data Outputs
: High-speed outputs to a hard disk drive or to a cable input.
FM_NODE[0]+
FM_NODE[0]-
FM_NODE[1]+
FM_NODE[1]-
FM_NODE[2]+
FM_NODE[2]-
FM_NODE[3]+
FM_NODE[3]-
FM_NODE[4]+
FM_NODE[4]-
FM_NODE[5]+
FM_NODE[5]-
FM_NODE[6]+
FM_NODE[6]-
FM_NODE[7]+
FM_NODE[7]-
16
15
26
25
29
28
38
37
41
40
51
50
54
53
63
62
HS_IN
Serial Data Inputs
: High-speed inputs from a hard disk drive or from a cable output.
BYPASS[0]-
BYPASS[1]-
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
BYPASS[5]-
BYPASS[6]-
BYPASS[7]-
13
24
30
36
42
49
55
1
I-LVTTL
Bypass Inputs
: For “disk bypassed” mode, connect BYPASS[n]- to GND through a1k
resistor.
For “disk in loop” mode, float HIGH.
REFCLK
2
I-LVTTL
Reference Clock
: A user-supplied clock reference used for frequency acquisition in
the Clock and Data Recovery (CDR) circuit.
CPLL1
CPLL0
10
11
C
Loop Filter Capacitor
: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit
must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1
μ
F.
FM_NODE[7]_AV
14
O-LVTTL
Amplitude Valid
: Indicates acceptable signal amplitude on the FM_NODE[7]
±
inputs.
If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1
If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable
If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-),
FM_NODE[7]_AV = 0
FM_NODE[0]_DV
4
O-LVTTL
Data Valid
: Indicates valid Fibre Channel Data on the FM_NODE[0]
±
inputs when HIGH. Indicates
either run length violation error or no comma detected when LOW.
RFCM
3
I-LVTTL
Reference Clock Mode
: To configure a one-twentieth-rate reference clock, connect RFCM to
GND through a 1k
resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH.
MODE_VDD
7
I_LVTTL
Valid Data Detect Mode
: To allow data valid detection, float MODE_VDD HIGH. To configure chip for
“CDR anywhere” capability, connect MODE_VDD to GND through a 1k
resistor.
FSEL
12
I_LVTTL
Frame Select
: To configure single-frame operation of the data valid and amplitude valid
detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame)
operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.
Table 3 is continued on next page.
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