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參數(shù)資料
| 型號： | HDMP-0482 |
| 英文描述： | Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
| 中文描述： | 八路細胞端口旁路電路CDR和數(shù)據(jù)有效檢測 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 149K |
| 代理商： | HDMP-0482 |
3
When the DV is configured in
single-frame mode (FSEL low),
any RLV and NCD errors stored
during this 2
15
bit interval cause
FM_NODE[0]_DV to be pulled
low on the next subsequent
interval. FM_NODE[0]_DV
remains low until after an entire
2
15
bit interval in which no RLVs
occur and at least one comma is
detected. At that time,
FM_NODE[0]_DV is pulled high.
A multi-frame mode (FSEL high)
configuration of the DV is also
available. When in multi-frame
mode, the FM_NODE[0]_DV
output is only pulled low when
four consecutive 2
15
bit intervals
of bad data have been transmit-
ted. Once low, FM_NODE[0]_DV
does not go high again until four
consecutive 2
15
bit intervals of
good data are transmitted.
AV Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[7]
±
is valid by exam-
ining the differential amplitude
of that input. The incoming data
is considered valid, and
FM_NODE[7]_AV is driven high,
as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[7]_AV
is driven low as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the ampli-
tude of the input signal is be-
tween 100
–
400 mV (differential
peak-to-peak), FM_NODE[7]_AV
is unpredictable. The
FM_NODE[7]_AV output is
latched in with an internally
generated 2
15
bit clock. Similar to
the DV function, the AV can be
configured for single-frame or
multi-frame operation.
BLL Output
All TO_NODE[n]
±
high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0482 are of
equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace. Unused outputs should not
be left unconnected. Ideally,
unused outputs should have their
differential pins shorted together
with a short PCB trace. If trans-
mission lines are connected to
the output pins, the lines should
be differentially terminated with
an appropriate resistor. The value
of the termination resistor should
match the PCB trace differential
impedance.
EQU Input
All FM_NODE[n]
±
high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs.
BYPASS[N]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0482. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1k
resistor. Other-
wise, the BYPASS[n]- inputs
should be left to float. In this
case, the internal pull-up cir-
cuitry will force them high.
REFCLK Input
The LVTTL REFCLK input
provides a reference oscillator
for frequency acquisition of the
CDR. The REFCLK frequency
should be within
±
100 ppm of
one-tenth or one-twentieth of the
incoming data rate in baud
(106.25 MHz
±
100 ppm, or
53.125 MHz
±
100 ppm for FC-AL
running at 1.0625 GBd).
RFCM Input
The LVTTL RFCM input config-
ures the CDR to accept a
REFCLK at either one-tenth or
one-twentieth of the incoming
data rate in baud. The RFCM
input has internal pull-up
circuitry, so the user should
connect the pin to GND through
a 1k
resistor for a REFCLK at
one-twentieth the incoming data
rate. For a REFCLK at one-tenth
the incoming data rate, let RFCM
float high.
MODE_VDD Input
The active high valid data detect
mode pin selects data checking of
the FM_NODE [0] +/- inputs.
When high, MODE_VDD overides
BYPASS [0] and forces the
incoming data into the CDR for
error checking. When low, the
chip can be configured for CDR
anywhere capability. Refer to
Figures 2 & 3 for high and low
MODE_VDD configuration.
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