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參數(shù)資料
| 型號(hào)： | HDMP-0482 |
| 英文描述： | Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
| 中文描述： | 八路細(xì)胞端口旁路電路CDR和數(shù)據(jù)有效檢測 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 149K |
| 代理商： | HDMP-0482 |
5
Table 1. Pin Connection Diagram to Achieve Desired CDR Location.
Hard Disk
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G
Connection to PBC Cell
1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4
CDR Position (x)
xA B C D E F G
AxB C D E F G
A BxC D E F G
A B CxD E F G
Cell Connection to Cable
0
7
6
5
Hard Disk
A B C D E F G
A B C D E F G
A B C D E F G
A B C D E F G
Connection to PBC Cell
5 6 7 0 1 2 3
4 5 6 7 0 1 2
3 4 5 6 7 0 1
2 3 4 5 6 7 0
CDR Position (x)
A B C DxE F G
A B C D ExF G
A B C D E FxG
A B C D E F Gx
Cell Connection to Cable
4
3
2
1
x denotes CDR position with respect to hard disks.
Figure 4. HDMP-0482 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code
(YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
BYPASS[7]-
REFCLK
RFCM
FM_NODE[0]_DV
VCC
GND
MODE_VDD
VCCA
GND
CPLL1
CPLL0
FSEL
BYPASS[0]-
FM_NODE[7]_AV
FM_NODE[0]-
FM_NODE[0]+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 5251 50 49
17 18 19 20 21 22 23 24 25 26 27 28 2930 31 32
VCCHS
TO_NODE[5]+
TO_NODE[5]-
VCCHS
TO_NODE[4]+
TO_NODE[4]-
BYPASS[4]-
FM_NODE[4]+
FM_NODE[4]-
GND
FM_NODE[3]+
FM_NODE[3]-
BYPASS[3]-
TO_NODE[3]+
TO_NODE[3]-
VCCHS
T
T
B
F
F
V
F
F
B
T
T
V
T
T
G
V
V
F
F
G
T
T
V
T
T
B
F
F
G
F
F
B
HDMP-0482
nnnn-nnn Rz.zz
S YYWW
Agilent
Table 2. I/O Type Definitions.
I/O Type
Definition
I-LVTTL
LVTTL Input
O-LVTTL
LVTTL Output
HS_OUT
High Speed Output, LVPECL Compatible
HS_IN
High Speed Input
C
External circuit node
S
Power supply or ground
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