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參數(shù)資料
| 型號(hào)： | HDMP-0422 |
| 英文描述： | Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops |
| 中文描述： | 單端口旁路電路的CDR |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 235K |
| 代理商： | HDMP-0422 |
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9
Guaranteed Operating Rates
V
CC
= 3.15 V to 3.45 V.
FC Serial Clock Rate (MBd)
Min.
1,040
GE Serial Clock Rate (MBd)
Min.
1,240
Max.
1,080
Max.
1,260
CDR Reference Clock Requirements
V
CC
= 3.15 V to 3.45 V.
Symbol Parameter
f
Nominal Frequency (Fibre Channel)
f
Nominal Frequency (Gigabit Ethernet)
F
tol
Frequency Tolerance
Symm
Symmetry (Duty Cycle)
Units
MHz
MHz
ppm
%
Min.
Typ.
106.25
125
Max.
–100
40
+100
60
Locking Characteristics
V
CC
= 3.15 V to 3.45 V.
Parameter
Bit Sync Time (phase lock)
Frequency Lock at Powerup
Units
bits
μ
s
Max.
2500
500
Figure 6. Eye diagram of TO_NODE[1]
±
high speed differential output (50
termination).
Note: Measurement taken with a 2
7
-1 PRBS input to FM_NODE[0]
±
Output Jitter Characteristics
V
CC
= 3.15 V to 3.45 V.
Symbol Parameter
RJ
[1]
Random Jitter at TO_NODE pins (1 sigma rms)
DJ
[1]
Deterministic Jitter at TO_NODE pins (pk-pk)
Units
ps
ps
Typ.
5
20
Max.
Note:
1. Please refer to Figures 7 and 8 for jitter measurement setup information.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0422G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0440 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| HDMP-0450 | 制造商:Agilent Technologies 功能描述: |
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
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