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參數(shù)資料
| 型號： | HDMP-0422 |
| 英文描述： | Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops |
| 中文描述： | 單端口旁路電路的CDR |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 235K |
| 代理商： | HDMP-0422 |
3
resistor. The value of the
termination resistor should match
the PCB trace differential
impedance.
EQU INPUT
All FM_NODE[n]
±
high-speed
differential inputs have an
Equalization (EQU) buffer to offset
the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs. The
value of the termination resistor
should match the PCB trace
differential impedance.
Alternatively, instead of a single
resistor, two resistors in series,
with an AC ground between them,
can be connected differentially
across the FM_NODE[n]
±
inputs.
The latter configuration attenuates
high-frequency common mode
noise.
BYPASS[n]- INPUT
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0422. All BYPASS pins are
LVTTL and contain internal pull-up
circuitry. To bypass a port, the
appropriate BYPASS[n]- pin should
be connected to GND through a 1
k
resistor. Otherwise, the
BYPASS[n]- inputs should be left to
float, as the internal pull-up
circuitry will force them high.
FM_NODE[0]_DV OUTPUT
The Data Valid (DV) block detects
if the incoming data at
FM_NODE[0]
is valid Fibre
Channel data. The DV block checks
for sufficient K28.5+ characters
(per Fibre Channel framing rules)
and for run length violations (per
8B/10B encoding) on the data
coming out of the CDR.
The FM_NODE[0]_DV output is
pulled low if a run length violation
(RLV) occurs, or if there are no
commas detected (NCD) over a
specific time interval. It is pulled
high if no errors are detected.
A RLV error is defined as any
consecutive sequence of 1s or 0s
greater than five in the serial bit
stream. An NCD error indicates the
absence of the seven-bit pattern
(0011111) present in the positive
disparity comma (K28.5+)
character. A K28.5+ character
should occur at the beginning of
every Fibre Channel frame of 2148
bytes (or 21480 serial bits), as well
as many times within and between
frames. If this seven-bit pattern is
not found within a 215 bit
(~31
μ
s) interval, an NCD error is
generated. A counter within the
chip tracks the 2
15
bit intervals.
Any RLV and NCD errors are
stored during the 2
15
bit interval.
The FM_NODE[0]_DV output is
pulled low at the start of the 2
15
bit
interval after errors are detected.
Once low, FM_NODE[0]_DV
remains in that state until an entire
2
15
bit interval has no RLV or NCD
errors. At the start of the 2
15
bit
interval subsequent to no RLV or
NCD errors being detected,
FM_NODE[0]_DV is pulled high.
MODE_DV INPUT
The active high Data Valid Mode
input selects Fibre Channel data
checking of the FM_NODE[0]
±
inputs. This is accomplished by
having MODE_DV override the
BYPASS[0]- control (see Figure 1),
thereby forcing the data into the
CDR to come from the
FM_NODE[0]
±
inputs. The
MODE_DV pin is an LVTTL input
and contains internal pull-up
circuitry. To select Data Valid
Mode, float MODE_DV high.
Otherwise, MODE_DV should be
connected to GND through a
1 k
resistor.
When MODE_DV is high, the user
is able to use the BYPASS[0]- input
to bypass invalid Fibre Channel
data from the rest of the loop. For
example, if FM_NODE[0]_DV is
connected to the BYPASS[0]-
input, data from the CDR will only
be routed to TO_NODE[1]
±
if the
data has no RLV or NCD errors. If
the DV block detects errors, the
signal at TO_NODE[0]
±
will be
routed to the TO_NODE[1]
±
outputs (see Figure 5).
FM_NODE[0]_AV OUTPUT
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[0]
±
is valid by
examining the differential
amplitude of that input. The
incoming data is considered valid,
and FM_NODE[0]_AV is driven
high, as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[0]_AV is
driven low as long as the amplitude
of the input signal is less than 100
mV (differential peak-to-peak).
When the amplitude of the input
signal is between 100-400 mV
(differential peak-to-peak), the
FM_NODE[0]_AV output is
undefined.
Table 1. Pin Connection Diagram to Achieve Desired CDR Location
(see Figures 2, 3)
Hard Disks
Connection to PBC cells
CDR position (x)
Cell connected to Cable
A
1
xA
0
A
0
Ax
1
x denotes CDR position with respect to hard disks.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0422G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0440 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| HDMP-0450 | 制造商:Agilent Technologies 功能描述: |
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
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