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參數(shù)資料
| 型號： | HDMP-0422 |
| 英文描述： | Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops |
| 中文描述： | 單端口旁路電路的CDR |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 235K |
| 代理商： | HDMP-0422 |
2
Figure 1. Block diagram of HDMP-0422.
training controls. It does this by
continually frequency locking
onto the 106.25 MHz reference
clock (REFCLK) and then phase
locking onto the input data
stream. Once bit locked, the CDR
generates a high-speed sampling
clock. This clock is used to
sample or repeat the incoming
data to produce the CDR output.
The CDR jitter specifications
listed in this data sheet assume
an input that has been 8B/10B
encoded. The CDR will also lock
onto data encoded using other
algorithms as long as there is DC
balance and a sufficient number
of transitions.
REFCLK INPUT
The LVTTL REFCLK input
provides a reference oscillator for
frequency acquisition of the CDR.
The REFCLK frequency should be
within
±
100 ppm of one-tenth of
the incoming data rate in baud
(106.25 MHz
±
100 ppm for FC-
AL running at 1.0625 GBd).
BLL OUTPUT
All TO_NODE[n]
±
high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0422 are
of equal strength and can drive
lengthy FR-4 PCB trace.
Unused outputs should not be left
unconnected. Ideally, unused
outputs should have their
differential pins shorted together
with a short PCB trace. If longer
traces or transmission lines are
connected to the output pins, the
lines should be differentially
terminated with an appropriate
The HDMP-0422 design allows for
CDR placement at any location
with respect to a hard disk slot.
For example, if hard disk A is
connected to PBC cell 1, while
BYPASS[0]- is left to float high
(see Figure 2), the CDR function
will be performed before entering
the hard disk at slot A. To obtain a
CDR function after slot A (see
Figure 3), connect hard disk A to
PBC cell 0, while floating
BYPASS[1]- high. Refer to Table 1
for both pin connections.
CDR
The Clock and Data Recovery
(CDR) block is responsible for
frequency and phase locking onto
the incoming serial data stream
and resampling the incoming data
based on the recovered clock. An
automatic locking feature allows
the CDR to lock onto the input
data stream without external
AV
CDR
CPLL
1
0
B
1
0
T
F
BLL
EQU
TTL
B
T
F
BLL
EQU
TTL
0
1
TTL
F
DV
F
TTL
R
TTL
M
TTL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0422G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0440 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| HDMP-0450 | 制造商:Agilent Technologies 功能描述: |
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
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