- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367058 > HDMP-0422 Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops PDF資料下載
參數(shù)資料
| 型號(hào)： | HDMP-0422 |
| 英文描述： | Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops |
| 中文描述： | 單端口旁路電路的CDR |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 235K |
| 代理商： | HDMP-0422 |
7
Pin Definitions
Pin Name
TO_NODE[0]+
TO_NODE[0]-
TO_NODE[1]+
TO_NODE[1]-
FM_NODE[0]+
FM_NODE[0]-
FM_NODE[1]+
FM_NODE[1]-
BYPASS[0]-
BYPASS[1]-
REFCLK
Pin
20
21
05
04
23
24
02
01
17
08
14
Pin Type
HS_OUT
Pin Description
Serial Data Outputs:
High-speed outputs to a hard disk drive or to a cable.
HS_IN
Serial Data Inputs:
High-speed inputs from a hard disk drive or from a cable.
I-LVTTL
Bypass Inputs:
For “disk bypassed” mode, connect BYPASS[n]- to GND through
a 1 k
resistor. For “disk in loop” mode, float HIGH.
Reference Clock:
A user-supplied clock reference used for frequency acquisition
in the Clock and Data Recovery (CDR) circuit.
Loop Filter Capacitor:
A loop filter capacitor for the internal Clock and Data
Recovery (CDR) circuit must be connected across the CPLL1 and CPLL0 pins.
Recommended value is 0.1
μ
F.
Data Valid:
Indicates Fibre Channel compliant data on FM_NODE[n]
±
inputs
when HIGH. Indicates either a run length violation or a no comma detected error
when LOW.
Data Valid Mode:
To allow data valid detection, float MODE_DV HIGH.
Otherwise, connect to GND through a 1 k
resistor.
Amplitude Valid:
Indicates acceptable signal amplitude on the FM_NODE[n]
±
inputs.
If (FM_NODE[n]+ – FM_NODE[n]-) >= 400 mV peak-to-peak,
FM_NODE[0]_AV = 1
If 400 mV > (FM_NODE[n]+ – FM_NODE[n]-) > 100 mV,
FM_NODE[0]_AV = undefined
If 100 mV >= (FM_NODE[n]+ – FM_NODE[n]-), FM_NODE[0]_AV = 0
Ground:
Normally 0 V. See Figure 13 for Recommended Power Supply Filtering.
I-LVTTL
CPLL1
CPLL0
12
13
C
FM_NODE[0]_DV
09
O-LVTTL
MODE_DV
11
I-LVTTL
FM_NODE[0]_AV
16
O-LVTTL
GND
06
07
18
19
15
S
V
CC
A
S
Analog Power Supply:
Normally 3.3 V. Used to provide a clean supply to the
Clock and Data Recovery (CDR) circuit. See Figure 13 for Recommended Power
Supply Filtering.
High Speed Supply:
Normally 3.3 V. Used only for high-speed outputs
(TO_NODE[n]). See Figure 13 for Recommended Power Supply Filtering.
Logic Power Supply:
Normally 3.3 V. Used for internal logic. See Figure 13 for
Recommended Power Supply Filtering.
V
CC
HS[0]
V
CC
HS[1]
V
CC
22
03
10
S
S
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HDNS-2100001 | Solid-State Optical Mouse Sensor |
| HDNS-2200001 | Solid-State Optical Mouse Sensor |
| HDP01-0512NRL | HARD DISK DRIVE POWER SUPPLY PROTECTION |
| HDP01-0512N | HARD DISK DRIVE POWER SUPPLY PROTECTION |
| HDSP-078X | Glass/Ceramic Numeric and Hexadecimal Displays for Industrial Applications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-0422G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0440 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops |
| HDMP-0450 | 制造商:Agilent Technologies 功能描述: |
| HDMP-0451 | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
| HDMP-0451G | 制造商:Rochester Electronics LLC 功能描述: 制造商:PMC-Sierra 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。