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參數(shù)資料
| 型號： | HB56UW3272ETK |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256MB Buffered EDO DRAM DIMM(256MB 緩沖 EDO DRAM DIMM) |
| 中文描述： | EDO公司的DRAM 256MB的內存緩沖（256MB的緩沖EDO公司的DRAM內存） |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 418K |
| 代理商： | HB56UW3272ETK |
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HB56UW3272ETK-F
12
19.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
20.t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
RAS
cycle (EDO
page mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater
than the specified t
(min) value. The value of
CAS
cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
21.Data output turns off and becomes high impedance from later rising edge of
RAS
and
CAS
.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS
between t
OHR
and t
OH
and between t
OFR
and t
OFF
.
22.t
defines the time at which the output level go cross. V
OL
= 0.8 V, V
OH
= 2.0 V of output timing
reference level.
23.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH
or V
IL
.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HB56UW3272ETK-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-5F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-6F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Buffered EDO DRAM DIMM 32-Mword × 72-bit, 4k Refresh, 2 Bank Module (36 pcs of 16M × 4 components) |
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