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參數(shù)資料
| 型號： | HB56UW3272ETK |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256MB Buffered EDO DRAM DIMM(256MB 緩沖 EDO DRAM DIMM) |
| 中文描述： | EDO公司的DRAM 256MB的內(nèi)存緩沖（256MB的緩沖EDO公司的DRAM內(nèi)存） |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 418K |
| 代理商： | HB56UW3272ETK |
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HB56UW3272ETK-F
11
EDO Page Mode Read-Modify-Write Cycle
50 ns
60 ns
Parameter
Symbol Min
Max
Min
Max
Unit
Notes
EDO page mode read- modify-write
cycle time
WE
delay time from
CAS
precharge
t
HPRWC
57
—
68
—
ns
t
CPW
45
—
54
—
ns
14
Refresh
Parameter
Symbol
Max
Unit
Notes
Refresh period
Notes: 1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh).
3. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RCD
(max) limit, than the access time is
controlled exclusively by t
CAC
.
4. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
OED
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
(min) and V
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
≤
t
(max) and t
≤
t
RAD
(max). If t
or t
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that t
RCD
≥
t
RCD
(max) and t
RCD
+ t
CAC
(max)
≥
t
RAD
+ t
AA
(max).
11.Assumes that t
RAD
≥
t
RAD
(max) and t
RCD
+ t
CAC
(max)
≤
t
RAD
+ t
AA
(max).
12.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13.t
(max), t
(max), t
(max) and t
(max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14.t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
≥
t
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min), and t
AWD
≥
t
AWD
(min), or t
CWD
≥
t
CWD
(min), t
AWD
≥
t
AWD
(min) and t
CPW
≥
t
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15.t
and t
are referred to
CAS
leading edge in early write cycles and to
WE
leading edge in
delayed write or read-modify-write cycles.
16.t
RASP
defines
RAS
pulse width in EDO page mode cycles.
17.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
18.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data
to the device.
t
REF
64
ms
4096 cycles
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB56UW3272ETK-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-5F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-6F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 EDO Page Mode DRAM Module |
| HB56UW3272ETK-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256MB Buffered EDO DRAM DIMM 32-Mword × 72-bit, 4k Refresh, 2 Bank Module (36 pcs of 16M × 4 components) |
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