參數(shù)資料
型號： HB52RD648DC-B
廠商： Elpida Memory, Inc.
英文描述： 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM
中文描述： 512 MB的無緩沖內(nèi)存的SODIMM 64 Mword】64位，133/100 MHz內(nèi)存總線，2銀模塊（16個32米】8部分）PC133/100 SDRAM內(nèi)存
文件頁數(shù)： 12/20頁
文件大?。?/td> 160K
代理商： HB52RD648DC-B
HB52RF648DC-B, HB52RD648DC-B
Data Sheet E0083H40
12
DC Characteristics
(Ta = 0 to +65
C, V
CC
, V
CC
Q = 3.3 V ± 0.3 V, V
SS
, V
SS
Q = 0 V)
HB52RF648DC/HB52RD648DC
-75
-A6
-B6
Parameter
Symbol Min
Max
Min
Max Min
Max Unit
Test conditions
Notes
Operating current
(
CE
latency = 2)
(
CE
latency = 3)
I
CC1
I
CC1
I
CC2P
—
1120
—
1000
—
840
mA
Burst length = 1
t
RC
= min
1, 2, 3
—
1120
—
1000
—
1000 mA
Standby current in
power down
—
48
—
48
—
48
mA
CKE = V
,
t
CK
= 12 ns
CKE = V
IL
, t
CK
=
∞
6
Standby current in
power down
(input signal stable)
I
CC2PS
—
32
—
32
—
32
mA
7
Standby current in non
power down
I
CC2N
—
320
—
320
—
320
mA
CKE,
S
= V
IH
,
t
CK
= 12 ns
CKE = V
,
t
CK
= 12 ns
CKE,
S
= V
IH
,
t
CK
= 12 ns
4
Active standby current
in power down
I
CC3P
—
64
—
64
—
64
mA
1, 2, 6
Active standby current
in non power down
I
CC3N
—
480
—
480
—
480
mA
1, 2, 4
Burst operating
current
(
CE
latency = 2)
(
CE
latency = 3)
I
CC4
—
1040
—
1040
—
840
mA
t
CK
= min, BL = 4
1, 2, 5
I
CC4
I
CC5
I
CC6
—
1320
—
1040
—
1040 mA
Refresh current
—
2000
—
2000
—
2000 mA
t
RC
= min
V
IH
≥
V
–
0.2 V
V
IL
≤
0.2 V
3
Self refresh current
—
48
—
48
—
48
mA
8
Self refresh current
(L-version)
I
CC6
—
32
—
32
—
32
mA
Input leakage current
I
LI
I
LO
–
10
10
–
10
10
–
10
10
μA
0
≤
Vin
≤
V
CC
0
≤
Vout
≤
V
CC
DQ = disable
Output leakage
current
–
10
10
–
10
10
–
10
10
μA
Output high voltage
V
OH
V
OL
2.4
—
2.4
—
2.4
—
V
I
OH
=
–
4 mA
I
OL
= 4 mA
Output low voltage
Notes: 1. I
depends on output load condition when the device is selected. I
CC
(max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
—
0.4
—
0.4
—
0.4
V
相關(guān)PDF資料
PDF描述
HB52RF649DC 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-A6B 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-A6BL 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-B 512MB Unbuffered SDRAM S.O.DIMM
HB52RF649DC-75B 512MB Unbuffered SDRAM S.O.DIMM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52RD648DC-B6B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD648DC-B6BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD649DC-A6B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-A6BL 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512MB Unbuffered SDRAM S.O.DIMM
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