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參數(shù)資料
| 型號： | HB52E649E12 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 512 MB Registered SDRAM DIMM(512 MB 寄存同步DRAM DIMM) |
| 中文描述： | 注冊使用512 MB SDRAM的內(nèi)存（512 MB的寄存同步的DRAM內(nèi)存） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 541K |
| 代理商： | HB52E649E12 |
HB52E649E12-A6B/B6B
5
19
SDRAM device attributes:
S latency
SDRAM device attributes:
W latency
SDRAM device attributes
SDRAM device attributes:
General
SDRAM cycle time
(2nd highest CE latency)
(-A6B) 10 ns
(-B6B) Undefined
SDRAM access from Clock
(2nd highest CE latency)
(-A6B) 6 ns
(-B6B) Undefined
SDRAM cycle time
(3rd highest CE latency)
Undefined
SDRAM access from Clock
(3rd highest CE latency)
Undefined
Minimum row precharge time
Row active to row active min
RE to CE delay min
Minimum RE pulse width
Density of each bank on module 1
0
0
0
0
0
0
0
1
01
0
20
0
0
0
0
0
0
0
1
01
0
21
22
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
16
0E
Registered
V
CC
±
10%
23
1
0
1
0
0
0
0
0
A0
CL = 2
*
7
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
00
60
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
25
26
0
0
0
0
0
0
0
0
00
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
14
14
14
32
80
20 ns
20 ns
20 ns
50 ns
1 bank
512M byte
2 ns*
7
32
Address and command signal
input setup time
Address and command signal
input hold time
Data signal input setup time
Data signal input hold time
36 to 61 Superset information
62
SPD data revision code
63
Checksum for bytes 0 to 62
(-A6B)
(-B6B)
64
Manufacturer’s JEDEC ID code 0
65 to 71 Manufacturer’s JEDEC ID code 0
72
Manufacturing location
0
0
1
0
0
0
0
0
20
33
0
0
0
1
0
0
0
0
10
1 ns*
7
34
35
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
20
10
00
12
1A
2 ns*
7
1 ns*
7
Future use
Rev. 1.2A
26
0
0
0
0
×
0
0
0
×
1
0
0
×
1
0
0
×
0
1
0
×
0
1
0
×
0
1
0
×
18
07
00
××
24
HITACHI
×
*
3
(ASCII-
8bit code)
H
B
5
2
E
73
74
75
76
77
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
48
42
35
32
45
Byte
No.
Function described
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Hex val-
ue
Comments
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| HB52F649E1 | 512 MB Registered SDRAM DIMM(512 MB 寄存同步DRAM DIMM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB52E649E12-A6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM |
| HB52E649E12-B6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Registered SDRAM DIMM 64-Mword 】 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M 】 4 Components) PC100 SDRAM |
| HB52E649EN-A6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus |
| HB52E649EN-B6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Unbuffered SDRAM DIMM, 100 MHz Memory Bus |
| HB52E88EM-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
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