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參數(shù)資料
| 型號： | GS9062-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進(jìn)程，商標(biāo)第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 41/46頁 |
| 文件大?。?/td> | 473K |
| 代理商： | GS9062-CFE3 |
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GS9062 Data Sheet
22209 - 5
May 2005
41 of 46
3.12 Device Power Up
Because the GS9062 is designed to operate in a multi-volt environment, any power
up sequence is allowed. The charge pump, phase detector, core logic, serial digital
output buffers and digital I/O buffers should all be powered up within 1ms of one
another.
Device pins may also be driven prior to power up without causing damage.
To ensure that all internal registers are cleared upon power-up, the application
layer must hold the
RESET_TRST
signal LOW for a minimum of 1ms after the core
power supply has reached the minimum level specified in the DC Electrical
Characteristics Table. See
Table 2-1
. See
Figure 3-12
.
3.13 Device Reset
In order to initialize all internal operating conditions to their default states the
application layer must hold the
RESET_TRST
signal LOW for a minimum of t
reset
=
1ms.
When held in reset, all device outputs will be driven to a high-impedance state.
Figure 3-12: Reset Pulse
CORE_VDD
RESET_TRST
t
reset
+1.65V
+1.8V
Reset
Reset
t
reset
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