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參數(shù)資料
| 型號： | GS9062-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進(jìn)程，商標(biāo)第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大小： | 473K |
| 代理商： | GS9062-CFE3 |
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GS9062 Data Sheet
22209 - 5
May 2005
23 of 46
3.2.4 Parallel Input Clock (PCLK)
The frequency of the PCLK input signal required by the GS9062 is determined by
the input data format.
Table 3-1
below lists the possible input signal formats and
their corresponding parallel clock rates. Note that DVB-ASI input will always be in
10-bit format, regardless of the setting of the 20bit/10bit pin.
3.3 SMPTE Mode
The GS9062 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M, and
NRZ-to-NRZI encoded prior to serialization.
3.3.1 Internal Flywheel
The GS9062 has an internal flywheel which is used in the generation of internal /
external timing signals, and in automatic video standards detection. It is
operational in SMPTE mode only.
The flywheel consists of a number of counters and comparators operating at video
pixel and video line rates. These counters maintain information about the total line
length, active line length, total number of lines per field / frame and total active lines
per field / frame for the received video standard.
When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied
H, V, and F timing signals.
Table 3-1: Parallel Data Input Format
Input Data Format
DOUT
[19:10]
DOUT
[9:0]
PCLK
Control Signals
20bit/10bit
SMPTE_BYPASS
DVB_ASI
SMPTE MODE
20bit DEMULTIPLEXED
LUMA
CHROMA
13.5MHz
HIGH
HIGH
LOW
10bit MULTIPLEXED
LUMA / CHROMA
HIGH IMPEDANCE
27MHz
LOW
HIGH
LOW
DVB-ASI MODE
10bit DVB-ASI
DVB-ASI DATA
HIGH IMPEDANCE
27MHz
HIGH
LOW
HIGH
DVB-ASI DATA
HIGH IMPEDANCE
27MHz
LOW
LOW
HIGH
DATA-THROUGH MODE
20bit DEMULTIPLEXED
DATA
DATA
13.5MHz
HIGH
LOW
LOW
10bit MULTIPLEXED
DATA
HIGH IMPEDANCE
27MHz
LOW
LOW
LOW
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