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參數(shù)資料
| 型號： | GS9062-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進(jìn)程，商標(biāo)第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 473K |
| 代理商： | GS9062-CFE3 |
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GS9062 Data Sheet
22209 - 5
May 2005
8 of 46
27
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select,
CS
, and is
active LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is
active HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
28
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output,
SDOUT, used to read status and configuration information from
the internal registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
29
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used
to write address and configuration information to the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
30
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK.
Command and data read/write words are clocked into the device
synchronously with this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the host interface is not being used, tie this pin HIGH.
32
BLANK
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable input data blanking.
When set LOW, the luma and chroma input data is set to the
appropriate blanking levels. Horizontal and vertical ancillary
spaces will also be set to blanking levels.
When set HIGH, the luma and chroma input data pass through
the device unaltered.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9064-CKD | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064-CKDE3 | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064A | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9074A | GS9074A HD-LINX-R II Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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