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參數(shù)資料
| 型號(hào)： | GS9062-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer |
| 中文描述： | GS9062的HD - LINX進(jìn)程，商標(biāo)第二SD - SDI和DVB - ASI在內(nèi)串行器 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 473K |
| 代理商： | GS9062-CFE3 |
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GS9062 Data Sheet
22209 - 5
May 2005
7 of 46
18
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device
will be configured to operate in SMPTE mode. All I/O processing
features may be enabled in this mode.
When set LOW, the device will not support the scrambling or
encoding of received SMPTE data. No I/O processing features
will be available.
19
RSET
Analog
Input
Used to set the serial digital output signal amplitude. Connect to
CD_VDD through 281
Ω
+/- 1% for 800mV
p-p
single-ended output
swing.
20
CD_VDD
–
Power
Power supply connection for the serial digital cable driver.
Connect to +1.8V DC analog.
21
SDO_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO
are disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO
are enabled.
22
CD_GND
–
Power
Ground connection for the serial digital cable driver. Connect to
analog GND.
23, 24
SDO, SDO
Analog
Output
Serial digital output signal operating at 270Mb/s.
The slew rate of these outputs is automatically controlled to meet
SMPTE 259M specifications.
25
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default
conditions and all input and output signals become high
impedance, including the serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default
and the JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence
resumes.
26
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and
SCLK_TCK are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and
SCLK_TCK are configured as GSPI pins for normal host
interface operation.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9064-CKD | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064-CKDE3 | GS9064 SD SDI Adaptive Cable Equalizer |
| GS9064A | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9074A | GS9074A HD-LINX-R II Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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