參數(shù)資料
型號： GS9062-CFE3
廠商： Gennum Corporation
英文描述： GS9062 HD-LINX-TM II SD-SDI and DVB-ASI Serializer
中文描述： GS9062的HD - LINX進程，商標第二SD - SDI和DVB - ASI在內(nèi)串行器
文件頁數(shù)： 31/46頁
文件大?。?/td> 473K
代理商： GS9062-CFE3
GS9062 Data Sheet
22209 - 5
May 2005
31 of 46
3.6.3.3 EDH Generation and Insertion
The GS9062 will generate and insert complete EDH packets into the data stream.
Packet generation and insertion will only take place if the EDH_CRC_INS bit of the
IOPROC_DISABLE register is set LOW.
The GS9062 will generate all of the required EDH packet data including all ancillary
data preambles, (DID, DBN, DC), reserved code words and checksum. Calculation
of both full field (FF) and active picture (AP) CRC's will be carried out by the device.
SMPTE RP165 specifies the calculation ranges and scope of EDH data for
standard 525 and 625 component digital interfaces. The GS9062 will utilize these
standard ranges by default.
If the received video format does not correspond to 525 or 625 digital component
video standards as determined by the flywheel pixel and line counters, then one of
two schemes for determining the EDH calculation ranges will be employed:
1. Ranges will be based on the line and pixel ranges programmed by the host
interface; or
2. In the absence of user-programmed calculation ranges, ranges will be
determined from the received TRS ID words or supplied H, V, and F timing
signals
Internal Flywheel on page 23
.
The registers available to the host interface for programming EDH calculation
ranges include active picture and full field line start and end positions for both
fields.
Table 3-8
shows the relevant registers, which default to '0' after device reset.
If any or all of these register values are zero, then the EDH CRC calculation ranges
will be determined from the flywheel generated H signal. The first active and full
field pixel will always be the first pixel after the SAV TRS code word. The last active
and full field pixel will always be the last pixel before the start of the EAV TRS code
words.
EDH error flags (EDH, EDA, IDH, IDA and UES) for ancillary data, full field and
active picture will also be inserted. These flags must be programmed into the
EDH_FLAG registers of the device by the application layer (
Table 3-9
).
NOTE 1: It is the responsibility of the user to ensure that the EDH flag registers are
updated once per field.
The prepared EDH packet will be inserted at the appropriate line of the video
stream according to RP165. The start pixel position of the inserted packet will be
based on the SAV position of that line such that the last byte of the EDH packet
(the checksum) will be placed in the sample immediately preceding the start of the
SAV TRS word.
NOTE 2: It is also the responsibility of the user to ensure that there is sufficient
space in the horizontal blanking interval for the EDH packet to be inserted.
相關(guān)PDF資料
PDF描述
GS9064-CKD GS9064 SD SDI Adaptive Cable Equalizer
GS9064-CKDE3 GS9064 SD SDI Adaptive Cable Equalizer
GS9064A GS9064A HD-LINX㈢ II Adaptive Cable Equalizer
GS9064ACKDE3 GS9064A HD-LINX㈢ II Adaptive Cable Equalizer
GS9074A GS9074A HD-LINX-R II Adaptive Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9064 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm
GS9064A 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer
GS9064ACKDE3 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer
GS9064ACTDE3 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer
GS9064-CKD 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*