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參數(shù)資料
| 型號： | GS815218 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（1M x 18Bit）S/DCD Burst SRAM(16M位（1M x 18位）可選單/雙循環(huán)取消同步靜態(tài)RAM（帶2位脈沖地址計數(shù)器）) |
| 中文描述： | 16Mb的（100萬x 18位）的S /雙氰胺突發(fā)靜態(tài)存儲器（1,600位（100萬× 18位），可選單/雙循環(huán)取消同步靜態(tài)隨機存儲器（帶2位脈沖地址計數(shù)器）） |
| 文件頁數(shù)： | 30/38頁 |
| 文件大小： | 824K |
| 代理商： | GS815218 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
30/38
2000, Giga Semiconductor, Inc.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1 compliant.
EXTEST (EXTEST-A)
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register, whatever length it may be in
the device, is loaded with all logic 0s. The EXTEST implementation in this device does not, without further user intervention, actually move
the contents of the scan chain onto the RAM’s output pins. Therefore, this device is not strictly 1149.1-compliant. Nevertheless, this RAM’s
TAP does respond to an all 0s instruction, EXTEST (000), by overriding the RAM’s control inputs and activating the Data I/O output drivers.
The RAM’s main clock (CK) may then be used to transfer Boundary Scan Register contents associated with each I/O from the scan register
to the RAM’s output drivers and onto the I/O pins. A single CK transition is sufficient to transfer the data, but more transitions will do no
harm.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST-A
000
Places the Boundary Scan Register between TDI and TDO.
This RAM implements an Clock Assisted EXTEST function. *Not 1149.1
Compliant *
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
This RAM does not implement 1149.1 PRELOAD function. *Not 1149.1
Compliant *
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
1
IDCODE
001
1, 2
SAMPLE-Z
010
1
RFU
011
1
SAMPLE/
PRELOAD
100
1
GSI
101
1
RFU
110
1
BYPASS
111
1
Notes:
1.
2.
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
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