參數(shù)資料
型號(hào)： GS815218
廠商： GSI TECHNOLOGY
英文描述： 16Mb（1M x 18Bit）S/DCD Burst SRAM(16M位（1M x 18位）可選單/雙循環(huán)取消同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）)
中文描述： 16Mb的（100萬(wàn)x 18位）的S /雙氰胺突發(fā)靜態(tài)存儲(chǔ)器（1,600位（100萬(wàn)× 18位），可選單/雙循環(huán)取消同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器））
文件頁(yè)數(shù)： 28/38頁(yè)
文件大小： 824K
代理商： GS815218
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
28/38
2000, Giga Semiconductor, Inc.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. Although the TAP controller in this device follows the 1149.1 conventions, it is not 1194.1
compliant because some of the mandatory instructions are uniquely implemented. The TAP on this device may be used to monitor
all input and I/O pads, but cannot be used to load address, data or control signals into the RAM or to preload the I/O buffers.This
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
1
1
0
0
0
0
10 9 8 7 6 5 4 3 2 1
0
x36
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
0 0 1 1 0 1 1 0 0 1
1
1
1
1
x32
x18
x16
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
· · ·
· · ·
n
0
1
2
0
1
2
· · ·
0
1
2
· · ·
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
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