參數(shù)資料
型號： GS815218
廠商： GSI TECHNOLOGY
英文描述： 16Mb（1M x 18Bit）S/DCD Burst SRAM(16M位（1M x 18位）可選單/雙循環(huán)取消同步靜態(tài)RAM（帶2位脈沖地址計數(shù)器）)
中文描述： 16Mb的（100萬x 18位）的S /雙氰胺突發(fā)靜態(tài)存儲器（1,600位（100萬× 18位），可選單/雙循環(huán)取消同步靜態(tài)隨機存儲器（帶2位脈沖地址計數(shù)器））
文件頁數(shù)： 1/38頁
文件大?。?/td> 824K
代理商： GS815218
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
1/38
2000, Giga Semiconductor, Inc.
Preliminary
GS815218/36/72B-225/200/180/166/150/133
1M x 18, 512K x 36, 256K x 72
16Mb S/DCD Sync Burst SRAMs
200 MHz
–
133MHz
3.3 V V
DD
2.5 V or 3.3 V I/O
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
FT pin for user-configurable flow through or pipeline operation
Single/Dual Cycle Deselect selectable
IEEE 1149.1 JTAG-compatible Boundary Scan
On-chip read parity checking; even or odd selectable
ZQ mode pin for user-selectable high/low output drive
On-chip parity encoding and error detection
3.3 V +10%/–5% core power supply
2.5 V or 3.3 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to SCD x18/x36 Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 119- and 209-bump BGA package
Functional Description
Applications
The GS815218/36/72B is a 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS815218/36/72B is a SCD (Single Cycle Deselect) and
DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
ByteSafe Parity Functions
The GS815218/36/72B features ByteSafe data security functions.
See the detailed discussion following.
FLXDrive
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS815218/36/72B operates on a 3.3 V power supply. All
input are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V- and 2.5 V-compatible.
-225 -200 -180 -166 -150 -133 Unit
7.0
8.5
205
240
325
285
285
285
2.5
4.4
350
410
570
515
470
435
Flow
Through
2-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
7.5
10.0
185
210
8.0
10.0
185
210
8.5
10.0
185
210
10.0
10.0
185
210
285
3.8
6.7
250
290
400
11.0
15.0
140
160
205
4.0
7.5
230
260
360
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Pipeline
3-1-1-1
3.0
5.0
315
370
3.2
5.5
290
340
3.5
6.0
270
315
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