參數(shù)資料
型號: GS1582
廠商: Gennum Corporation
英文描述: IC,MC14490P
中文描述: 多速率的電纜驅(qū)動(dòng)器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù): 79/114頁
文件大?。?/td> 1224K
代理商: GS1582
GS1582 Data Sheet
40117 - 1 November 2007
79 of 114
Figure 4-29: GSPI Read Mode Timing
Figure 4-30: GSPI Write Mode Timing
Table 4-41: GSPI Timing Parameters
Parameter
Definition
Specification
t
0
The minimum duration of time chip select, CS, must be
LOW before the first SCLK rising edge.
1.5 ns
t
1
The minimum SCLK period.
100 ns
t
2
Duty cycle tolerated by SCLK.
40% to 60%
t
3
Minimum input setup time.
1.5 ns
t
4
Write Cycle: the minimum duration of time between the
last SCLK command (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word.
37.1 ns
t
5
Read Cycle: the minimum duration of time between the
last SCLK command (or data word if the Auto-Increment
bit is HIGH) and the first SCLK of the data word.
148.4 ns
t
6
Minimum output hold time.
1.5 ns
t
7
The minimum duration of time between the last SCLK of
the GSPI transaction and when CS can be set HIGH.
37.1 ns
t
8
Minimum input hold time.
1.5 ns
SCLK
CS
SDIN
SDOUT
t
5
t
6
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
R/W
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
3
SCLK
CS
SDIN
SDOUT
t
0
t
1
t
2
t
4
R/W
RSV
RSV
AutoInc
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
RSV
RSV
AutoInc
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
7
t
8
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