參數(shù)資料
型號: GS1582
廠商: Gennum Corporation
英文描述: IC,MC14490P
中文描述: 多速率的電纜驅(qū)動器,音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁數(shù): 34/114頁
文件大小: 1224K
代理商: GS1582
GS1582 Data Sheet
40117 - 1 November 2007
34 of 114
Figure 4-8: HSYNC:VSYNC:DE Input Timing 720 (1440) x 576 @ 50
4.4 DVB-ASI mode
The GS1582 operates in DVB-ASI mode when the SMPTE_BYPASS pin is set
LOW and the DVB_ASI and SD/HD pins are set HIGH.
In this mode, all SMPTE processing functions are disabled, and the 8-bit transport
stream data will be 8b/10b encoded prior to serialization.
4.4.1 Control Signal Inputs
In DVB-ASI mode, the DIN19 and DIN18 pins are configured as DVB-ASI control
signals INSSYNCIN and KIN respectively.
When INSSYNCIN is set HIGH, the device will insert K28.5 sync characters into
the data stream. This function is used in system implementations where the
GS1582 is preceded by an external data FIFO. Parallel DVB-ASI data may be
clocked into the FIFO at some rate less than 27MHz. The INSSYNCIN input may
then be connected to the FIFO empty signal, providing a means of padding the
data transmission rate to 27MHz. See
Figure 4-9
.
1728 Total Horizontal Clocks per line
Data
Enable
HSYNC
126
1440 Clocks for Active Video
288
24
138 clocks
1728 clocks
24
HSYNC
VSYNC
288 Active Vertical Lines per field
Data
Enable
623 624 625 1 2 3 4 5 6 7 22 23 310 311 312
Field 1: 24 Vertical Blanking Lines
864
1728 clocks
HSYNC
VSYNC
Data
Enable
310 311 312 313 314 315 316 317 318 319 320 335 336 623 624 625
Field 2: 25 Vertical Blanking Lines
~
~
~
~
~
~
~
~
264
264
~
~
~
~
~
~
~
~
288 Active Vertical Lines per field
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