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| 型號(hào)： | GS1582 |
| 廠商： | Gennum Corporation |
| 英文描述： | IC,MC14490P |
| 中文描述： | 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行 |
| 文件頁(yè)數(shù)： | 75/114頁(yè) |
| 文件大小： | 1224K |
| 代理商： | GS1582 |
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GS1582 Data Sheet
40117 - 1 November 2007
75 of 114
40KHz by varying the loop filter resistor, as shown in
Table 4-40: Loop Filter
Component Values
. For use with the GEN-Clocks
TM
timing generators, a narrow
loop bandwidth is recommended.
Increasing the loop filter capacitor value increases the stability of the PLL, but
results in a longer lock time. For loop filter resistors smaller than 7
Ω
, a capacitor
value of 33μF is recommended, while larger resistor values can accommodate
smaller capacitors. Sample combinations of the loop filter resistor and capacitor
values are shown in
Table 4-40: Loop Filter Component Values
, along with the
resulting loop bandwidth. Additional loop bandwidths can be achieved by using
different loop filter resistor values.
4.11.3 Lock Detect Output
The LOCKED output will be asserted HIGH when the internal PLL has locked to
the input PCLK signal. In the absence of the PCLK, when frequency lock has not
been achieved, and during device reset, the LOCKED output will be LOW.
Lock time, the time it takes for the internal PLL to frequency-lock to the reference
PCLK following power-up or standby, is determined by the loop filter capacitor
value chosen. A 1
μ
F loop filter capacitor, for example, will result in lock times of
less than 500
μ
s. A 33
μ
F loop filter capacitor, on the other hand, will result in a lock
time of greater than 5s.
NOTE 1: When the PLL is in the process of locking to the reference PCLK, the
LOCKED pin may generate LOW and HIGH pulses. The durations of these pulses
are dependent on the loop filter capacitor value, but do not exceed 30ms. Once the
PLL has achieved frequency lock, the LOCKED pin will remain HIGH and not
change state.
NOTE 2: When the GS1582 is placed in standby mode, the value of LOCKED is
maintained although the PLL does lose lock to the reference PCLK. When
STANDBY is released, the PLL will re-lock. During this time, if the LOCKED pin
was previously HIGH, it will de-assert approximately 6
μ
s later, and re-assert once
the PLL has re-locked to the input PCLK.
Table 4-40: Loop Filter Component Values
Loop Filter
Resistor
Value
Typical Loop
Bandwidth*
Recommended
Loop Filter
Capacitor
Value
Comments
1
Ω
2kHz
33
μ
F
Narrow bandwidth - provides
maximum jitter reduction. Long
lock-time.
7
Ω
8kHz
10
μ
F
20
Ω
40kHz
1
μ
F
Wide bandwidth. Fast lock-time.
* Measured with 300ps pk-pk input jitter on PCLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1582_09 | 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleaner |
| GS1582-IBE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類(lèi)型:串行 輸出類(lèi)型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| GS-158N | 制造商:Taiyo Electric Ind. 功能描述: |
| GS15A | 制造商:MEANWELL 制造商全稱(chēng):Mean Well Enterprises Co., Ltd. 功能描述:7.2~15WAC-DC Single Output Desktop |
| GS15A/B | 功能描述:插入式交流適配器 RoHS:否 制造商:Phihong 地區(qū):Universal 安裝風(fēng)格:Wall, Interchangeable Plug 輸入電壓范圍:90 VAC to 264 VAC 輸出端數(shù)量:1 輸出功率額定值:5 W 輸出電壓（通道 1）:5 V 輸出電流（通道 1）:1 A 直流輸出連接器:USB Type A 隨附/必需的交流插頭:Required 商用/醫(yī)用:Commercial 效率:Level V |
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