參數(shù)資料
型號(hào)： GS1582
廠商： Gennum Corporation
英文描述： IC,MC14490P
中文描述： 多速率的電纜驅(qū)動(dòng)器，音頻多路復(fù)用器和ClockCleaner⑩串行
文件頁(yè)數(shù)： 69/114頁(yè)
文件大?。?/td> 1224K
代理商： GS1582
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GS1582 Data Sheet
40117 - 1 November 2007
69 of 114
4.9.4.1 SMPTE 352M Payload Identifier Packet Insertion
The GS1582 can generate and insert SMPTE 352M payload identifier ancillary
data packets.
When this feature is enabled, the device will automatically generate the ancillary
data preambles, (DID, SDID, DBN, DC), and calculate the checksum. The SMPTE
Table 4-35: Host Interface Description for Internal Processing Disable Register
Register Name
Bit
Name
Description
R/W
Default
IOPROC_DISABLE
Address: 000h
15-13
–
Not Used. Set to zero.
–
0
12
TIM_861_PIN_EN
Setting this bit LOW allows the timing mode to be
selectable through the CEA_861bit. Setting this bit
HIGH allows the timing mode to be selectable
through the CEA_861 bit, regardless of the pin
setting.
R/W
0
11
ANC_INS
Enable or disable ancillary data insertion. Set LOW
for enable. Set HIGH for disable.
R/W
0
10
AUDIO_EMBED
Disable audio embedding.
R/W
0
9
CEA_861
CEA_861 pin override bit. Active when
TIM_861_PIN_EN bit is set HIGH. Set CEA_861 bit
LOW to enable CEA 861 timing. Set this bit HIGH to
disable CEA 861 timing.
R/W
0
8
H_CONFIG
Horizontal blanking timing configuration. Set LOW
when the H/HSYNC input timing is based on active
line blanking (default). Set HIGH when the H input
timing is based on the H bit of the TRS words. See
Figure 4-2
.
R/W
0
7
–
Not Used. Set to zero.
–
0
6
352M_INS
SMPTE352M packet insertion. In HD mode, 352M
packets are inserted in the luma channel only when
one of the bytes in the VIDEO_FORMAT_A or
VIDEO_FORMAT_B registers are programmed with
non-zero values. Set HIGH to disable.
R/W
0
5
ILLEGAL_REMAP
Illegal Code Remapping. Detection and correction
of illegal code words within the active picture area
(AP). Set HIGH to disable.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical
Redundancy Check (CRC) error correction. In SD
mode the GS1582 will generate and insert EDH
packets. Set HIGH to disable.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Checksum insertion. Set HIGH to
disable.
R/W
0
2
CRC_INS
Luma and chroma line-based CRC insertion. In HD
mode, line-based CRC words are inserted in both
the luma and chroma channels. Set HIGH to disable
R/W
0
1
LNUM_INS
Luma and chroma line number insertion - HD mode
only. Set HIGH to disable.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. Set HIGH to
disable.
R/W
0
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