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參數(shù)資料
| 型號(hào)： | GS1561-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器 |
| 文件頁(yè)數(shù)： | 69/80頁(yè) |
| 文件大小： | 842K |
| 代理商： | GS1561-CFE3 |
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GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
69 of 80
Figure 3-10: Command Word
Figure 3-11: Data Word
3.12.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown in
Figure 3-12
and
Figure 3-13
respectively. The maximum SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the data word may be
presented to SDIN immediately following the falling edge of the LSB of the
command word. All SDIN data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of the data word will be
available on SDOUT 12ns following the falling edge of the LSB of the command
word, and thus may be read by the host on the very next rising edge of the clock.
The remaining bits are clocked out by the GS1560A on the negative edges of
SCLK.
Figure 3-12: GSPI Read Mode Timing
Figure 3-13: GSPI Write Mode Timing
R/W
RSV
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
MSB
LSB
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
MSB
LSB
SDOUT
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
t
5
t
6
output data
hold time
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
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