- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384345 > GS1561-CFE3 (Gennum Corporation) GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer PDF資料下載
參數(shù)資料
| 型號(hào)： | GS1561-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器 |
| 文件頁數(shù)： | 36/80頁 |
| 文件大?。?/td> | 842K |
| 代理商： | GS1561-CFE3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
36 of 80
In slave mode, the application layer fixes the center frequency of the reclocker such
that the lock algorithm will attempt to lock within the single data rate determined by
the setting of the SD/HD pin. Asynchronous lock times are also listed in the
Table
2-2: AC Electrical Characteristics
.
NOTE: The PCLK output will continue to operate during the lock detection process.
The frequency may toggle between 148MHz and 27MHz when the 20bit/10bit pin
is set LOW, or between 74MHz and 13.5MHz when 20bit/10bit is set HIGH.
For SMPTE and DVB-ASI inputs, the lock detect block will only assert the LOCKED
output signal HIGH if (1) the reclocker has locked to the input data stream as
indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have
been correctly identified.
If after four attempts lock has not been achieved, the lock detection algorithm will
enter into PLL lock mode. In this mode, the reclocker will attempt to lock to the input
data stream without detecting SMPTE TRS or DVB-ASI sync words. This
unassisted process can take up to 10ms to achieve lock.
When reclocker lock as indicated by the internal pll_lock signal is achieved in this
mode, one of the following will occur:
1. In slave mode, data will be passed directly to the parallel outputs without any
further processing taking place and the LOCKED signal will be asserted HIGH
if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW; or
2. In master mode, the LOCKED signal will be asserted LOW, the parallel
outputs will be latched to logic LOW, and the SMPTE_BYPASS and DVB_ASI
output signals will also be set LOW.
3.6.2 Master Mode
Recall that the GS1560A/GS1561 is said to be in master mode when the
MASTER/SLAVE input signal is set HIGH. In this case, the following four device
pins become output status signals:
The combined setting of these pins will indicate whether the device has locked to
valid SMPTE or DVB-ASI data at SD or HD rates.
Table 3-2
shows the possible
combinations.
SMPTE_BYPASS
DVB_ASI
SD/HD
RC_BYP (GS1560A only)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1574-CNE3 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1575A | GS1575A / GS9075A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1563 | 制造商:Thomas & Betts 功能描述:Installing Dies |
| GS1567 | 制造商:P&B 功能描述:5945-00-9151610 |
| GS1572-IBE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。