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參數(shù)資料
| 型號： | GS1561-CFE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer |
| 中文描述： | GS1560A/GS1561的HD - LINX進程- R的第二雙率解串器 |
| 文件頁數(shù)： | 65/80頁 |
| 文件大?。?/td> | 842K |
| 代理商： | GS1561-CFE3 |
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GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
65 of 80
3.11 Parallel Data Outputs
Data outputs leave the device on the rising edge of PCLK as shown in
Figure 3-7
and
Figure 3-8
.
The data may be scrambled or unscrambled, framed or unframed, and may be
presented in 10-bit or 20-bit format. The output data bus width is controlled
independently from the internal data bus width by the 20bit/10bit input pin.
Likewise, the output data format is defined by the setting of the external SD/HD,
SMPTE_BYPASS and DVB_ASI pins. Recall that in slave mode, these pins are set
by the application layer as inputs to the device. In master mode, however, the
GS1560A sets these pins as output status signals.
3.11.1 Parallel Data Bus Buffers
The parallel data outputs of the GS1560A/GS1561 are driven by high-impedance
buffers which support both LVTTL and LVCMOS levels. These buffers use a
separate power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins.
All output buffers, including the PCLK output, may be driven to a high-impedance
state if the RESET_TRST signal is asserted LOW.
Note that the timing characteristics of the parallel data output buffers are optimized
for 10-bit HD operation. As shown in
Figure 3-7
, the output data hold time for HD
is 1.5ns.
Due to this optimization, however, the output data hold time for SD data is so small
that the rising edge of the PCLK is nearly incident with the data transition. To
improve output hold time at SD rates, the PCLK output is inverted is SD mode,
(SD/HD = HIGH). This is shown in
Figure 3-8
.
Figure 3-7: HD PCLK to Data Timing
PCLK
DOUT[19:0]
DATA
Control signal
output
t
OH
t
OD
HD MODE
相關PDF資料 |
PDF描述 |
|---|---|
| GS1574A | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574ACNE3 | GS1574A HD-LINX-R II Adaptive Cable Equalizer |
| GS1574 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1574-CNE3 | GS1574 HD-LINX -TM II Adaptive Cable Equalizer |
| GS1575A | GS1575A / GS9075A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS1561-CFT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1561-CFTE3 | 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru |
| GS1563 | 制造商:Thomas & Betts 功能描述:Installing Dies |
| GS1567 | 制造商:P&B 功能描述:5945-00-9151610 |
| GS1572-IBE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應商設備封裝:64-TQFP-EP（10x10） 包裝:管件 |
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