參數(shù)資料
型號(hào)： GS1561-CFE3
廠商： Gennum Corporation
英文描述： GS1560A/GS1561 HD-LINX-R II Dual-Rate Deserializer
中文描述： GS1560A/GS1561的HD - LINX進(jìn)程- R的第二雙率解串器
文件頁(yè)數(shù)： 11/80頁(yè)
文件大?。?/td> 842K
代理商： GS1561-CFE3
GS1560A/GS1561 Data Sheet
27360 - 8
September 2005
11 of 80
21
SDO_EN/DIS
Non
Synchronous
Input
GS1560A
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
NC
–
–
GS1561
No Connect.
22
CD_GND
–
Power
GS1560A
Ground connection for the serial digital cable driver. Connect to analog
GND.
NC
–
–
GS1561
No Connect.
23, 24
SDO, SDO
Analog
Output
GS1560A
Serial digital loop-through output signal operating at 1.485Gb/s,
1.485/1.001Gb/s, or 270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M specifications according to the setting of the SD/HD pin.
NC
–
–
GS1561
No Connect.
25
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
impedance, including the
serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
NOTE: When in slave mode, reset the device after the SD/
HD
input has
been initially configured, and after each subsequent SD/HD data rate
change.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
26
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料
PDF描述
GS1574A GS1574A HD-LINX-R II Adaptive Cable Equalizer
GS1574ACNE3 GS1574A HD-LINX-R II Adaptive Cable Equalizer
GS1574 GS1574 HD-LINX -TM II Adaptive Cable Equalizer
GS1574-CNE3 GS1574 HD-LINX -TM II Adaptive Cable Equalizer
GS1575A GS1575A / GS9075A HD-LINX-R II Multi-Rate SDI Automatic Reclocker
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS1561-CFT 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述:
GS1561-CFTE3 制造商:Semtech Corporation 功能描述:Receiver for HD/SD/ASI w/out loop thru
GS1563 制造商:Thomas & Betts 功能描述:Installing Dies
GS1567 制造商:P&B 功能描述:5945-00-9151610
GS1572-IBE3 功能描述:RF, RFID, WIRELESS RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*