參數(shù)資料
型號(hào): GS1535
英文描述: Multi-rate Reclocker for HD-SDI. SD-SDI & DVB-ASI. 3.3V supply.
中文描述: 多速率時(shí)鐘恢復(fù)器的HD - SDI的。標(biāo)清SDI
文件頁(yè)數(shù): 34/39頁(yè)
文件大?。?/td> 631K
代理商: GS1535
GENNUM CORPORATION
21498-1
34 of 39
G
3.10.1 Command Word Description
The command word is transmitted MSB first and contains a
read/write bit, nine reserved bits and a 6-bit register
address. Set R/W = '1' to read and R/W = '0' to write from
the GSPI.
Command words are clocked into the GS1532 on the rising
edge of the serial clock SCLK. The appropriate chip select
signal, CS, must be asserted low a minimum of 1.5ns (t0 in
Figure 14 and Figure 15) before the first clock edge to
ensure proper operation.
Each command word must be followed by only one data
word to ensure proper operation.
Figure 12 Command Word
Figure 13 Data Word
3.10.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown
in Figure 14 and Figure 15 respectively. The maximum
SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the
data word may be presented to SDIN immediately following
the falling edge of the LSB of the command word. All SDIN
data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of
the data word will be available on SDOUT 12ns (t5)
following the falling edge of the LSB of the command word,
and thus may be read by the host on the very next rising
edge of the clock. The remaining bits are clocked out by
the GS1532 on the negative edges of SCLK.
Figure 14 GSPI Read Mode Timing
Figure 15 GSPI Write Mode Timing
R/W
RSV
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
MSB
LSB
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
MSB
LSB
SDOUT
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
t
5
t
6
output data
hold time
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
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