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參數(shù)資料
| 型號： | GS1535 |
| 英文描述： | Multi-rate Reclocker for HD-SDI. SD-SDI & DVB-ASI. 3.3V supply. |
| 中文描述： | 多速率時鐘恢復(fù)器的HD - SDI的。標(biāo)清SDI |
| 文件頁數(shù)： | 32/39頁 |
| 文件大?。?/td> | 631K |
| 代理商： | GS1535 |
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GENNUM CORPORATION
21498-1
32 of 39
G
3.6.3.4 Ancillary Data Checksum Generation and Insertion
The GS1532 will calculate checksums for all detected
ancillary data packets presented to the device. These
calculated checksum values are inserted into the data
stream prior to serialization.
Ancillary data checksum generation and insertion will only
take
place
if
the
ANC_CSUM_INS
IOPROC_DISABLE register is set LOW.
bit
of
the
3.6.3.5 Line Based CRC Generation and Insertion
The GS1532 will generate and insert line based CRC words
into both the Y and C channels of the data stream. This
feature is only available in HD mode and is enabled by
setting the CRC_INS bit of the IOPROC_DISABLE register
LOW.
3.6.3.6 HD Line Number Generation and Insertion
In HD mode, the GS1532 will calculate and insert line
numbers into the Y and C channels of the output data
stream.
Line number generation is in accordance with the relevant
HD video standard as determined by the device, (see
Section 3.6.2).
This feature is enabled when SD/HD = LOW, and the
LNUM_INS bit of the IOPROC_DISABLE register is set LOW.
3.6.3.7 TRS Generation and Insertion
The GS1532 can generate and insert 10-bit TRS code
words into the data stream as required. This feature is
enabled
by
setting
the
IOPROC_DISABLE register LOW.
TRS_INS
bit
of
the
TRS word generation will be performed in accordance with
the timing parameters generated by the flywheel which will
be locked either to the received TRS ID words or the
supplied H, V, and F timing signals (see Section 3.3.1).
3.7 PARALLEL-TO-SERIAL CONVERSION
The parallel data output of the internal data processing
blocks is fed to the parallel-to-serial converter. The function
of this block is to generate a serial data stream from the 10-
bit or 20-bit parallel data words and pass the stream to the
integrated cable driver.
3.8 SERIAL DIGITAL DATA PLL
To obtain a clean clock signal for serialization and
transmission, the input PCLK is locked to an external
reference signal via the GS1532's integrated phase-locked
loop. This PLL is also responsible for generating all internal
clock signals required by the device.
Internal division ratios for the locked PCLK are determined
by the setting of the SD/HD and 20bit/10bit pins as shown
in Table 10.
3.8.1 External VCO
The GS1532 requires the GO1525 external voltage
controlled oscillator as part of its internal PLL.
Power for the external VCO is generated entirely by the
GS1532 from an integrated voltage regulator. The internal
regulator uses +3.3V supplied on the CP_VDD / CP_GND
pins to provide +2.5V on the VCO_VCC / VCO_GND pins.
The external VCO produces a 1.485GHz reference signal
for the PLL, input on the VCO pin of the device. Both
reference and control signals should be referenced to the
supplied VCO_GND as shown in the recommended
application circuit of Section 4.1.
3.8.2 Lock Detect Output
The lock detect block controls the serial digital output signal
and indicates to the application layer the lock status of the
device via the LOCKED output pin.
LOCKED will be asserted HIGH if and only if the internal
data PLL has locked the PCLK signal to the external VCO
reference signal and one of the following is true:
1. The device is set to operate in SMPTE mode and has
detected SMPTE TRS words in the serial stream; or
2. The device is set to operate in DVB-ASI mode and has
detected K28.5 sync characters in the serial stream; or
3. The device is set to operate in Data-Through mode.
TABLE 10 SERIAL DIGITAL OUTPUT RATES
PIN SETTINGS
SUPPLIED
PCLK RATE
SERIAL DIGITAL
OUTPUT RATE
SD/HD
20
bit
/10
bit
LOW
HIGH
74.25 or
74.25/1.001 MHz
1.485 or
1.485/1.001Gb/s
LOW
LOW
148.5 or
148.5/1.001MHz
1.485 or
1.485/1.001Gb/s
HIGH
HIGH
13.5MHz
270Mb/s
HIGH
LOW
27MHz
270Mb/s
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PDF描述 |
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| GS1560A* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| GS1561* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| GS15T48-5 | 15W DC-DC CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1535A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
| GS1535A_06 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
| GS1535ACFUE3 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
| GS1535BCFUE3 | 制造商:Gennum Corporation 功能描述:IC RELOCKER HD/SD/ASI 64LQFP 制造商:Gennum Corporation 功能描述:IC, RELOCKER, HD/SD/ASI, 64LQFP 制造商:Gennum Corporation 功能描述:IC, RELOCKER, HD/SD/ASI, 64LQFP; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:64; Operating Temperature Min:0C; Operating Temperature Max:70C; MSL:MSL 3 - 168 hours; SVHC:No SVHC |
| GS1535-CFU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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