參數(shù)資料
型號： GS1535
英文描述： Multi-rate Reclocker for HD-SDI. SD-SDI & DVB-ASI. 3.3V supply.
中文描述： 多速率時鐘恢復(fù)器的HD - SDI的。標(biāo)清SDI
文件頁數(shù)： 27/39頁
文件大?。?/td> 631K
代理商： GS1535
GENNUM CORPORATION
21498-1
27 of 39
G
3.6.3 Packet Generation and Insertion
In addition to input data blanking and automatic video
standards detection, the GS1532 may also calculate,
assemble and insert into the data stream various types of
ancillary data packets and TRS ID words.
These features are only available when the device is set to
operated in SMPTE mode and the IOPROC_EN/DIS pin is
set HIGH. Individual insertion features may be enabled or
disabled via the IOPROC_DISABLE register (Table 5).
All of the IOPROC_DISABLE register bits default to '0' after
device reset, enabling all of the processing features. To
disable any individual error correction feature, the host
interface must set the corresponding bit HIGH in this
register.
TABLE 5 HOST INTERFACE DESCRIPTION FOR INTERNAL PROCESSING DISABLE REGISTER
REGISTER NAME
BIT
NAME
DESCRIPTION
R/W
DEFAULT
IOPROC_DISABLE
Address: 000h
15-9
Not Used
8
H_CONFIG
Horizontal sync timing input configuration. Set LOW when
the H input timing is based on active line blanking (default).
Set HIGH when the H input timing is based on the H bit of
the TRS words. See Figure 8.
R/W
0
7
Not Used
6
352M_INS
SMPTE352M packet insertion. In HD mode, 352M packets
are inserted in the Y channel only when the four
VIDEO_FORMAT_IN registers are programmed with non-
zero values. The IOPROC_EN/DIS pin and SMPTE_BYPASS
pin must also be set HIGH. Set HIGH to disable.
R/W
0
5
ILLEGAL_REMAP
Illegal Code Remapping. Detection and correction of illegal
code words within the active picture area (AP). The
IOPROC_EN/DIS pin and SMPTE_BYPASS pin must also be
set HIGH. Set HIGH to disable.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction. In SD mode the GS1532 will
generate and insert EDH packets. The IOPROC_EN/DIS pin
and SMPTE_BYPASS pin must also be set HIGH. Set HIGH
to disable.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Checksum insertion. The IOPROC_EN/DIS
pin and SMPTE_BYPASS pin must also be set HIGH. Set
HIGH to disable.
R/W
0
2
CRC_INS
Y and C line-based CRC insertion. In HD mode, line-based
CRC words are inserted in both the Y and C channels. The
IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be also
set HIGH. Set HIGH to disable
R/W
0
1
LNUM_INS
Y and C line number insertion - HD mode only. The
IOPROC_EN/DIS pin and SMPTE_BYPASS pin must be set
HIGH. Set HIGH to disable.
R/W
0
0
TRS_INS
Timing Reference Signal Insertion. Occurs only when
IOPROC_EN/DIS is HIGH and SMPTE_BYPASS is HIGH. Set
HIGH to disable.
R/W
0
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