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參數(shù)資料
| 型號(hào)： | GS1532* |
| 英文描述： | Serializer for HD-SDI. SD-SDI & DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 序列化的HD - SDI信號(hào)。標(biāo)清SDI |
| 文件頁數(shù)： | 8/39頁 |
| 文件大?。?/td> | 631K |
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GENNUM CORPORATION
21498-1
8 of 39
G
34
F
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS
signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
The F signal should be set HIGH for the entire period of field 2 and should
be set LOW for all lines in field 1 and for all lines in progressive scan
systems.
The F signal is ignored when DETECT_TRS = HIGH.
35
V
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking when DETECT_TRS is set LOW. The device will set the V
bit in all outgoing TRS signals for the entire period that the V input signal is
HIGH (IOPROC_EN/DIS must also be HIGH).
The V signal should be set HIGH for the entire vertical blanking period and
should be set LOW for all lines outside of the vertical blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
36
H
Synchronous
with PCLK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data
when DETECT_TRS is set LOW. The device will set the H bit in all outgoing
TRS signals for the entire period that the H input signal is HIGH
(IOPROC_EN/DIS must also be HIGH).
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
h
)
The H signal should be set HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal should be set HIGH for the entire horizontal blanking period
as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
37, 64
CORE_VDD
-
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1535 | Multi-rate Reclocker for HD-SDI. SD-SDI & DVB-ASI. 3.3V supply. |
| GS1560A* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| GS1561* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| GS15T48-5 | 15W DC-DC CONVERTER |
| GS15T48 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1532_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1532-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1532-CFE3 | 制造商:Gennum Corporation 功能描述:Multi Rate Serializer 80-Pin LQFP |
| GS1535 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
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