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參數(shù)資料
| 型號(hào)： | GS1532* |
| 英文描述： | Serializer for HD-SDI. SD-SDI & DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 序列化的HD - SDI信號(hào)。標(biāo)清SDI |
| 文件頁數(shù)： | 29/39頁 |
| 文件大?。?/td> | 631K |
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GENNUM CORPORATION
21498-1
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3.6.3.2 Illegal Code Remapping
If the ILLEGAL_REMAP bit of the IOPROC_DISABLE
register is set LOW, the GS1532 will remap all codes within
the active picture between the values of 3FCh and 3FFh to
3FBh. All codes within the active picture area between the
values of 000h and 003h will be remapped to 004h.
In addition, 8-bit TRS and ancillary data preambles will be
remapped to 10-bit values if this feature is enabled.
3.6.3.3 EDH Generation and Insertion
When operating in SD mode, (SD/HD = HIGH), the GS1532
will generate and insert complete EDH packets into the
data stream. Packet generation and insertion will only take
place if the EDH_CRC_INS bit of the IOPROC_DISABLE
register is set LOW.
The GS1532 will generate all of the required EDH packet
data including all ancillary data preambles, (DID, DBN,
DC), reserved code words and checksum. Calculation of
both full field (FF) and active picture (AP) CRC's will be
carried out by the device.
SMPTE RP165 specifies the calculation ranges and scope
of EDH data for standard 525 and 625 component digital
interfaces. The GS1532 will utilize these standard ranges by
default.
If the received video format does not correspond to 525 or
625 digital component video standards as determined by
the flywheel pixel and line counters, then one of two
schemes for determining the EDH calculation ranges will be
employed:
1. Ranges will be based on the line and pixel ranges
programmed by the host interface; or
2. In the absence of user-programmed calculation ranges,
ranges will be determined from the received TRS ID
words or supplied H, V, and F timing signals (see
Section 3.3.1).
The registers available to the host interface for
programming EDH calculation ranges include active picture
and full field line start and end positions for both fields.
Table 8 shows the relevant registers, which default to '0'
after device reset.
If any or all of these register values are zero, then the EDH
CRC calculation ranges will be determined from the
flywheel generated H signal. The first active and full field
pixel will always be the first pixel after the SAV TRS code
word. The last active and full field pixel will always be the
last pixel before the start of the EAV TRS code words.
EDH error flags (EDH, EDA, IDH, IDA and UES) for ancillary
data, full field and active picture will also be inserted. These
flags must be programmed into the EDH_FLAG registers of
the device by the application layer (Table 9).
NOTE 1: It is the responsibility of the user to ensure that the
EDH flag registers are updated once per field.
The prepared EDH packet will be inserted at the
appropriate line of the video stream according to RP165.
The start pixel position of the inserted packet will be based
on the SAV position of that line such that the last byte of the
EDH packet (the checksum) will be placed in the sample
immediately preceding the start of the SAV TRS word.
NOTE 2: It is also the responsibility of the user to ensure
that there is sufficient space in the horizontal blanking
interval for the EDH packet to be inserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1535 | Multi-rate Reclocker for HD-SDI. SD-SDI & DVB-ASI. 3.3V supply. |
| GS1560A* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI with loop thru cable driver. 3.3/1.8V supply. |
| GS1561* | Reclocking deserializer for HD-SDI. SD-SDI & DVB-ASI without loop thru cable driver. 3.3/1.8V supply. |
| GS15T48-5 | 15W DC-DC CONVERTER |
| GS15T48 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1532_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate Serializer with ClockCleaner |
| GS1532-CF | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1532-CFE3 | 制造商:Gennum Corporation 功能描述:Multi Rate Serializer 80-Pin LQFP |
| GS1535 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
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