參數(shù)資料
型號(hào): GS1532*
英文描述: Serializer for HD-SDI. SD-SDI & DVB-ASI. 3.3/1.8V supply.
中文描述: 序列化的HD - SDI信號(hào)。標(biāo)清SDI
文件頁數(shù): 10/39頁
文件大小: 631K
GENNUM CORPORATION
21498-1
10 of 39
G
51, 52,
54–59, 62,
63
DIN[10:19]
Synchronous
with PCLK
Input
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN19 is the MSB and DIN10 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI
modeSMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS
= HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS
= LOW
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS
= LOW
DVB_ASI = HIGH
67
DETECT_TRS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the timing mode of the device.
When set HIGH, the device will lock the internal flywheel to the embedded
TRS timing signals in the parallel input data.
When set LOW, the device will lock the internal flywheel to the externally
supplied H, V, and F input signals.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
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