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| 型號： | GM2125 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 48/54頁 |
| 文件大小： | 1339K |
| 代理商： | GM2125 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
46
C2115-DAT-01B
Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of
bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the
most significant bit (MSB) first. After the eight data bits, the master releases the HFSn line
and the receiver asserts the HFSn line low to acknowledge receipt of the data. The master
device generates the HCLK pulse during the acknowledge cycle. The addressed receiver is
obliged to acknowledge each byte that has been received.
The Write Address Increment and the Write Address No Increment operations allow one or
multiple registers to be programmed with only sending one start address. In Write Address
Increment, the address pointer is automatically incremented after each byte has been sent and
written. The transmission data stream for this mode is illustrated in Figure 30 below. The
highlighted sections of the waveform represent moments when the transmitting device must
release the HFSn line and wait for an acknowledgement from the gm2115/25 (the slave
receiver).
ACK
ACK
ACK
OPERATION CODE
START
HFSn
HCLK
STOP
DEVICE ADDRESS
REGISTER ADDRESS
DATA
DATA
R/W
ACK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
9
A8
Two MSBs of register address
A9
Figure 30.
2-Wire Write Operations (0x1x & 0x2x)
The Read Address No Increment (0xA0) operation is illustrated in Figure 31. The highlighted
sections of the waveform represent moments when the transmitting device must release the
HFSn line and waits for an acknowledgement from the master receiver.
Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
DATA
DEVCEADDRESS
DATA
DATA
START
ACK
ACK
OPERATONCODE
START
HFSn
HCLK
STOP
DEVCEADDRESS
REGSTERADDRESS
RW
ACK
RW
ACK
ACK
Figure 31.
2-Wire Read Operation (0xAx)
Please note that in all the above operations the operation code includes two address bits, as
described in Table 17.
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