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參數(shù)資料
| 型號(hào)： | GM2125 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 32/54頁 |
| 文件大?。?/td> | 1339K |
| 代理商： | GM2125 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
30
C2115-DAT-01B
4.10.1 Display Synchronization
Refer to section 4.1 for information regarding internal clock synthesis.
The gm2115/25 supports the following display synchronization modes:
Frame Sync Mode:
The display frame rate is synchronized to the input frame or
field rate. This mode is used for standard operation.
Free Run Mode:
No synchronization. This mode is used when there is no valid input
timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In
free-run mode, the display timing is determined only by the values programmed into
the display window and timing registers.
4.10.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control
signals. The figure below provides the registers that define the output display timing.
Horizontal values are programmed in single-pixel increments relative to the leading edge of
the horizontal sync signal. Vertical values are programmed in line increments relative to the
leading edge of the vertical sync signal.
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