參數(shù)資料
型號(hào)： GM2125
廠商： Electronic Theatre Controls, Inc.
英文描述： ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER
中文描述： 模擬國(guó)際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器
文件頁(yè)數(shù)： 47/54頁(yè)
文件大?。?/td> 1339K
代理商： GM2125
***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
45
C2115-DAT-01B
Table 17. Instruction Byte Map
Operation Mode
Bit
7 6 5 4 3 2 1 0
0 0 0 1 x x A9 A8
0 0 1 0 x x A9 A8
Description
Write Address Increment
Write Address No Increment
(for table loading)
Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to
increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.
1 0 0 1 x x A9 A8
1 0 1 0 x x A9 A8
Reserved
Read Address No Increment
(for table reading)
0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8
Reserved
Spare
No operation will be performed
4.15.2 2-wire Serial Protocol
The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional
serial data line HFSn (pin number 205). The bus master drives HCLK and either the master
or slave can drive the HFSn line (open drain) depending on whether a read or write operation
is being performed. The gm2115/25 operates as a slave on the interface.
The 2-wire protocol requires each device be addressable by a 7-bit identification number.
The gm2115/25 is initialized on power-up to 2-wire mode by asserting bootstrap pins
HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the
rising edge of RESETn (see Table 16). This provides flexibility in system configuration with
multiple devices that can have the same address.
A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in
the figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while
HCLK is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn
while HCLK is held high) or by a START (to begin another transfer). The HFSn signal must
be stable when HCLK is high, it may only change when HCLK is low (to avoid being
misinterpreted as START or STOP).
ADDRESS BYTE
HFSn
1
2
3
7
8
9
HCLK
4
5
6
1
2
8
9
DATA BYTE
ACK
ACK
START
STOP
Receiver acknowledges by holding SDA low
R/W
A6
A1
A2
A3
A4
A5
A0
D6
D7
D0
Figure 29.
2-Wire Protocol Data Transfer
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