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參數(shù)資料
| 型號： | GM2125 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 27/54頁 |
| 文件大?。?/td> | 1339K |
| 代理商： | GM2125 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
25
C2115-DAT-01B
VSYNC timing. However, the gm2115/25 provides an internal HSYNC and VSYNC delay
feature that removes this limitation. This feature is available for use with the ADC input. By
delaying the sync internally, the gm2115/25 can capture data that spans across the sync pulse.
It is possible to use HSNYC and VSYNC delay for image positioning. (Alternatively,
Source_HSTART and Source_VSTART in Figure 12 are used for image positioning of
analog input.) Taken to an extreme, the intentional movement of images across apparent
HSYNC and VSYNC boundaries creates a horizontal and/or vertical wrap effect.
HSYNC is delayed by a programmed number of selected input clocks.
HS(system)
active
active
capture
HS(internal)
capture
capture
programmable
delay
input block actually
captures across HSYNC
Figure 14.
HSYNC Delay
Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with
respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but
with different paths to the gm2115/25 (HSYNC is often regenerated from a PLL). As a
result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line
counter and HSYNC is used to increment it, any difference in the relative position of
HSYNC and VSYNC is seen on-screen as vertical jitter. By delaying the HSYNC a small
amount, it can be ensured that VSYNC always resets the line counter prior to it being
incremented by the “first” HSYNC.
delayed HS placed safely within blanking
active data crosses HS boundary
Data
HS (system)
Internal Delayed HS
Figure 15.
Active Data Crosses HSYNC Boundary
4.5.2 Horizontal and Vertical Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC
signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal
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