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參數(shù)資料
| 型號： | GM2125 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ANALOG INTER FACE XGA/SXGA ONPANEL LCD PANEL CONTROLLER |
| 中文描述： | 模擬國際米蘭的XGA / SXGA ONPANEL液晶顯示器控制器 |
| 文件頁數(shù)： | 10/54頁 |
| 文件大?。?/td> | 1339K |
| 代理商： | GM2125 |
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***
Genesis Microchip Confidential ***
gm2115/25 Preliminary Data Sheet
June 2002
8
C2115-DAT-01B
3. GM2115/25 PIN LIST
I/O Legend: A
= Analog,
I
= Input,
O
= Output,
P
= Power,
G
= Ground
Table 1. Analog Input Port
No. I/O Description
Pin Name
AVDD_RED
172
AP
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to
AGND_RED pin on system board (as close as possible to the pin).
Positive analog input for Red channel.
Negative analog input for Red channel.
Analog ground for the red channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to
AGND_GREEN pin on system board (as close as possible to the pin).
Positive analog input for Green channel.
Negative analog input for Green channel.
Analog ground for the green channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to
AGND_BLUE pin on system board (as close as possible to the pin).
Positive analog input for Blue channel.
Negative analog input for Blue channel.
Analog ground for the blue channel.
Must be directly connected to the analog system ground plane.
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).
Analog test output for ADC Do not connect.
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.
Dedicated pad for substrate guard ring that protects the ADC reference system.
Must be directly connected to the analog system ground plane.
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND1_ADC pin on system board (as close as possible to the pin).
Digital GND for ADC clocking circuit.
Must be directly connected to the digital system ground plane.
Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to
GND2_ADC pin on system board (as close as possible to the pin).
ADC input horizontal sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
ADC input vertical sync input.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
RED+
RED-
AGND_RED
171
170
169
AI
AI
AG
AVDD_GREEN
168
AP
GREEN+
GREEN-
AGND_GREEN
167
166
165
AI
AI
AG
AVDD_BLUE
164
AP
BLUE+
BLUE-
AGND_BLUE
163
162
161
AI
AI
AG
AVDD_ADC
160
AP
ADC_TEST
AGND_ADC
159
158
AO
AG
SGND_ADC
157
AG
GND1_ADC
156
G
VDD1_ADC_2.5
155
P
GND2_ADC
154
G
VDD2_ADC_2.5
153
P
HSYNC
137
I
VSYNC
136
I
Table 2. RCLK PLL Pins
No I/O Description
Pin Name
AVDD_RPLL
150
AP
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-
ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 13.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
AVSS_RPLL
149
AG
TCLK
152
AI
XTAL
VDD_RPLL
VSS_RPLL
151
148
147
AO
P
G
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