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參數(shù)資料
| 型號： | GL800HT25 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 UTMI Compliant Transceiver IP Core |
| 中文描述： | 采用UTMI兼容的USB 2.0收發(fā)器IP核 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 172K |
| 代理商： | GL800HT25 |
GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
2000-2003 Genesys Logic Inc.—All rights reserved.
Page 9
3.2 Block Diagram
HS
DLL
Elasticity
Buffer
M
U
X
NRZI
Decoder
Bit
Unstuffer
Rcv
Status/
Control
Xmit
HS XCVR
Rx
Register
Parallel
Rx Data
Receive
State
Machine
Transmit
State
Machine
Tx
Register
Parallel
Tx Data
Bit
Stuffer
NRZI
Encoder
Clock
Multiplier
Control
Logic
Control
CLK
External
Crystal
FS DLL
& Data
Recovery
Rcv
Status/
Control
Xmit
FS XCVR
Data+
Data-
Analog Front End
Figure 3.2 - Block Diagram
1. HS XCVR
HS XCVR contains the low-level analog circuitry required to physically interface USB 2.0 signaling to the
USB DP/DM signal lines.
2. FS XCVR
FS XCVR includes the logic necessary to send and receive the FS data on USB.
3. Clock Multiplier
Clock Multiplier generates the internal clocks for the GL800HT25 USB 2.0 Transceiver and the CLK30
signal. All data transfer signals are synchronized with the CLK30 signal.
In HS mode there is one clock cycle per byte time. The frequency of clock does not change when the UTMI
is switched between HS to FS modes. In FS mode there are 5 clock cycles per FS bit time, typically 40
clock cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be
stretched to 45 clock cycles, and two stuffed bits would result in a 50 clock delay between bytes.
4. HS DLL
(High Speed Delay Line PLL)
DLL extracts clock and data from the data received over the USB 2.0 interface for reception by the Receive
Deserializer. The data output from the DLL is synchronous with the local clock.
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