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參數(shù)資料
| 型號： | GL800HT25 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 UTMI Compliant Transceiver IP Core |
| 中文描述： | 采用UTMI兼容的USB 2.0收發(fā)器IP核 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 172K |
| 代理商： | GL800HT25 |
GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
2000-2003 Genesys Logic Inc.—All rights reserved.
Page 14
data for next transfer on the Data bus. If TXVLD is asserted and
TXRDY is negated, the SIE must hold the previously asserted data
on the Data bus. From the time TXVLD is negated, TXRDY is a
don’t care for the SIE.
D0~D15
27~30,
33~40,
43~46
31
B
Data bus 0~15
DVDD0
P
Positive digital supply (3.3V)
Positive digital supply
UMC 0.35um sample : 3.3V
TSMC 0.25um sample : 2.5V
Digital ground (0V)
Line State. These signals reflect the current state of the single
ended receivers. They are combinatorial until a “usable” CLK30 is
available then they are synchronized to CLK30. They directly
reflect the current state of the DP (LineState[0]) and DM
(LineState[1]) signals:
DM DP Description
0 1 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
DVDD1
41
P
DGND0~1
32,42
P
LINEST1
47
O
LINEST0
48
O
Notation:
Type
O
I
B
B/I
B/O
P
A
SO
pu
pd
odpu
Output
Input
Bi-directional
Bi-directional, default input
Bi-directional, default output
Power / Ground
Analog
Automatic output low when suspend
Internal pull up
Internal pull down
Open drain with internal pull up
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