參數(shù)資料
型號(hào)： GL800HT25
廠商： Genesys Logic, Inc.
英文描述： USB 2.0 UTMI Compliant Transceiver IP Core
中文描述： 采用UTMI兼容的USB 2.0收發(fā)器IP核
文件頁數(shù)： 4/20頁
文件大?。?/td> 172K
代理商： GL800HT25
GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
2000-2003 Genesys Logic Inc.—All rights reserved.
Page 4
TABLE OF CONTENTS
CHAPTER 1 GENERAL DESCRIPTION........................................................................6
CHAPTER 2 FEATURES...................................................................................................7
CHAPTER 3 BLOCK DIAGRAM.....................................................................................8
3.1 S
YSTEM
C
ONFIGURATION
..............................................................................................8
3.2 B
LOCK
D
IAGRAM
...........................................................................................................9
CHAPTER 4 PIN ASSIGNMENT....................................................................................11
4.1 P
INOUTS
.......................................................................................................................11
4.2 P
IN
L
IST
........................................................................................................................12
4.3 P
IN
D
ESCRIPTIONS
.......................................................................................................12
CHAPTER 5 FUNCTIONAL DESCRIPTION...............................................................15
5.1 T
RANSMIT
O
PERATION
................................................................................................15
5.1.1 Transmit State Diagram.....................................................................................15
5.1.2 Transmit Timing for Data Packet.....................................................................16
5.2 R
ECEIVE
O
PERATION
..................................................................................................16
5.2.1 Receive State Diagram .......................................................................................16
5.2.2 Receive Timing for Data Packet (with CRC-16)..............................................17
5.3 T
IMING
C
HART
............................................................................................................18
5.3.1 CLK30 Rising and Falling Edge VS. Input/Output Signals...........................18
5.3.2 Relationship Between Mode Change and Other Input Signals......................19
CHAPTER 6 PACKAGE DIMENSION..........................................................................20
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