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參數(shù)資料
| 型號(hào)： | GL800HT25 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 UTMI Compliant Transceiver IP Core |
| 中文描述： | 采用UTMI兼容的USB 2.0收發(fā)器IP核 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 172K |
| 代理商： | GL800HT25 |
GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
2000-2003 Genesys Logic Inc.—All rights reserved.
Page 17
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RXACTV and RXVLD are sampled on the rising edge of CLK30.
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In the RX Wait state the receiver is always looking for SYNC.
z
The Macrocell asserts RXACTV when SYNC is detected (Strip SYNC state).
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The Macrocell negates RXACTV when an EOP is detected (Strip EOP state).
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When RXACTV is asserted, RXVLD will be asserted if the RX Holding Register is full.
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RXVLD will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
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The SIE must be ready to consume a data byte if RXACTV and RXVLD are asserted (RX Data state).
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In FS mode, if a bit stuff error is detected then the Receive State Machine will negate RXACTV and
RXVLD, and return to the RXWait state.
5.2.2 Receive Timing for Data Packet (with CRC-16)
Figure 5.4 - Timing Diagram of Receive for Data Packet (with CRC-16)
Note that the USB 2.0 transceiver does not decode Packet ID’s (PIDs). They are passed to the SIE for
decoding.
This timing example is in HS mode. When a HS/FS UTM is in FS mode there are approximately 40 clock
cycles every byte time. The Receive State Machine assumes that the SIE captures the data on the data bus if
RXACTV and RXVLD are asserted. In FS mode, RXVLD will only be asserted for one clock per byte time.
Note that the receive and transmit sections of the transceiver operate independently. The receiver will receive
any packets on the USB. The transceiver does not identify whether the packet that it is receiving from the
upstream or the downstream port. The SIE must ignore receive data while it is transmitting.
Data
Data
Data
Data
CRC
CRC
PID
SYNC
PID
Data
Data
Data
Data
CRC
CRC
EOP
CLK30
RXACTV
Data
RXVLD
RXERR
DP/DM
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