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參數(shù)資料
| 型號(hào)： | GL800HT25 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 UTMI Compliant Transceiver IP Core |
| 中文描述： | 采用UTMI兼容的USB 2.0收發(fā)器IP核 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | GL800HT25 |
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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
2000-2003 Genesys Logic Inc.—All rights reserved.
Page 7
CHAPTER 2 FEATURES
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Complies with Universal Serial Bus Specification Rev. 2.0.
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Complies with USB 2.0 Transceiver Macrocell Interface (UTMI) Specification.
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Supports 480 Mbit/s "High Speed" (HS) / 12 Mbit/s “Full Speed” (FS), FS Only serial data transmission
rates.
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16 bit Bi-directional Serial Interface Engine (SIE) bus.
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SYNC/EOP generation and checking.
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Supports “Chirp” for High Speed recognition.
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Data and clock recovery from serial stream on the USB.
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Bit-stuffing / unstuffing; Bit stuff error detection.
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Holding registers to stage transmit and receive data.
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Supports Reset and Suspend.
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Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.
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Available in 48 pin LQFP package or IP macrocell on the 0.35μm UMC / 0.25μm TSMC standard CMOS
processes.
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