參數(shù)資料
型號: FT232HQ-REEL
廠商: FTDI, Future Technology Devices International Ltd
文件頁數(shù): 33/65頁
文件大?。?/td> 0K
描述: IC HS USB TO UART/FIFO 48QFN
應(yīng)用說明: FT1248 Application Note
標(biāo)準(zhǔn)包裝: 1
通道數(shù): 1,UART
FIFO's: 4kb
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 1.98 V,2.97 V ~ 3.63 V
帶并行端口:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(8x8)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 768-1102-6
Copyright 2012 Future Technology Devices International Limited
39
Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.8
Clearance No.: FTDI #199
4.9.1 Outgoing Fast Serial Data
To send fast serial data out of the FT232H, the external device must drive the FSCLK clock. If the FT232H
has data ready to send, it will drive FSDO output low to indicate the start bit. It will not do this if it is
currently receiving data from the external device. This is illustrated in Figure 4.18
Figure 4.18 Fast Serial Interface Output Data
Notes :-
1. The first bit output (Start bit) is always 0.
2. FSDO is always sent LSB first.
3. The last serial bit output is the source bit (SRCE) is always 0.
4. If the target device is unable to accept the data when it detects the START bit, it should stop the
FSCLK until it can accept the data.
4.9.2 Incoming Fast Serial Data
An external device is allowed to send data into the FT232H if FSCTS is high. On receipt of a zero START
bit on FSDI, the FT232H will drop FSCTS on the next positive clock edge. The data from bits 0 to 7 are
then clocked in (LSB first). The last bit (DEST) determines where the data will be written to. This bit is
always 0 with the FT232H. This is illustrated in Figure 4.19
Figure 4.19 Fast Serial Interface Input Data
Notes:-
1. The first bit input (Start bit) is always 0.
2. FSDI is always received LSB first.
3. The last received serial bit is the destination bit (DEST) is always 0.
4.
The target device should ensure that FSCTS is high before it sends data. FSCTS goes low after
data bit 0 (D0) and stays low until the chip can accept more data.
FSCLK
FSDO
0
D0
D1
D2
D3
D4
D5
D6
D7
SRCE
Start
Bit
Data Bits - LSB first
Source
Bit
FSCLK
FSDI
0
D0
D1
D2
D3
D4
D5
D6
D7
DEST
Start
Bit
Data Bits - LSB first
Destination
Bit
FSCTS
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